Monte Carlo Simulation Study of Local Critical Dimension Error on Mask and Wafer

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概要

• 論文の詳細を見る

• Sub-100 nm lithography has been realized recently in the IC industry. The resolution enhancement techniques (RET) and optical proximity effect correction (OPC) require more complicated mask patterns. It is therefore, very important to simulate and calculate mask error enhanced factor (MEEF), and critical dimension (CD) variations on the mask and wafer correctly using optical simulation tool before manufacturing. However, the expectations of MEEF and CD error using the in-house optical simulation tool, Topo, are larger than those of the experimental result. These are caused by many reasons. The ignorance of the vector property of light could be one reason. In case of using higher numerical aperture (NA), the vector property of light, such as polarization, should be taken into account when calculation of printed image on wafer. Also, the ignorance of the local CD error caused by the neighborhood could be another reason. The second issue described above has been studied using the Monte Carlo (MC) method, a commonly used statistical method. We assume that all of the factors follow the normal curve with a certain standard deviation. This assumption is sufficient for studying local CD error by the MC method. When the local CD variation on the mask for the design rule 110 nm is 3 nm in its $3\sigma$, CD variation of approximately 2.0 nm on wafer is expected by the MC method. This result is fairly comparable with experimental one, when the MEEF is about 2.7 locally. We obtain another MEEF value, around 4.1 globally, when the mask CD deviates from the target CD by $\pm 12$ nm in $3\sigma$. This study shows that the MC method gives a result close to that of the experimental one greater than 2.5 of MEEF locally.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2004-06-15

著者

• Ahn Byoung-sup

  Semiconductor R&d Center Samsung Electronics Co. Ltd.

• Sohn Jung-min

  Semicodutor R&d Center Samsung Electronics

• Park Joon-soo

  Semiconductor R&d Center Samsung Electronics Co. Ltd.

• Choi Seong-woon

  Semicodutor R&d Center Samsung Electronics

• Choi Seong-Woon

  Semiconductor R&D Center, Samsung Electronics Co., Ltd., San No24, Nongseo, Giheung, Yongin, 449-711, South Korea

• Ahn Byoung-sup

  Semiconductor R&D Center, Samsung Electronics Co., Ltd., San No24, Nongseo, Giheung, Yongin, 449-711, South Korea

• Sohn Jung-Min

  Semiconductor R&D Center, Samsung Electronics Co., Ltd., San No24, Nongseo, Giheung, Yongin, 449-711, South Korea

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• Monte Carlo Simulation Study of Local Critical Dimension Error on Mask and Wafer
• Monte Carlo Simulation Study of Local Critical Dimension Error on Mask and Wafer

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