Effective hardware task context switching in Virtex-4 FPGAs (VLSI設計技術)

概要

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A unique aspect of flexibility provided by some of the FPGAs such as Xilinx Virtex-4 family is the capability of dynamic and partial reconfiguration, giving them additional leverage over the other co-existing FPGA solutions by allowing implementation of such concepts as a hardware task. When compared to classical software task effective employment of the new idea in preemptive multitasking systems poses many difficulties and involves many mechanisms such as context saving and restoring, to be built practically from the scratch. This paper presents an effective approach to high-speed context switching for Virtex4-based DPR (Dynamic Partial Reconfiguration) Systems based on developed embedded system infrastructure with lightweight control bus, enhancing management of reconfigurable hardware modules and very efficient, instruction-driven reconfigurationlreadback controller which offers 78-fold speed-ups and further superior functionalities when compared to baseline IP provided by FPGA's manufacturer. The whole system is additionally supported by developed bitstream manipulation tool intended for PC (Personal Computer) and used as a back-end program for current DPR design flow.
2010-01-19