Impacts of Compiler Optimizations on Address Bus Energy : An Empirical Study(VLSI Design Technology and CAD)
スポンサーリンク
概要
- 論文の詳細を見る
Energy consumption is one of the most critical constraints in the design of portable embedded systems. This paper describes an empirical study about the impacts of compiler optimizations on the energy consumption of the address bus between processor and instruction memory. Experiments using a number of real-world applications are presented, and the results show that transitions on the instruction address bus can be significantly reduced (by 85% on the average) by the compiler optimizations together with bus encoding.
- 社団法人電子情報通信学会の論文
- 2004-10-01
著者
-
TOMIYAMA Hiroyuki
Department of Pblymer Science and Engineering, Faculty of Engineering, Yamagata University
-
Tomiyama Hiroyuki
Graduate School Of Information Science Nagoya University
-
Tomiyama Hiroyuki
The Department Of Computer Science And Communication Engineering Graduate School Of Information Scie
-
Tomiyama Hiroyuki
The Interdisciplinary Graduate School Of Engineering Sciences Kyushu University
-
Tomiyama H
Department Of Information Engineering The Graduate School Of Information Science Nagoya University
-
Takada H
Department Of Information Engineering The Graduate School Of Information Science Nagoya University
-
Tomiyama Hiroyuki
Department Of Information Engineering The Graduate School Of Information Science Nagoya University
関連論文
- Effective hardware task context switching in Virtex-4 FPGAs (VLSI設計技術)
- Effective hardware task context switching in Virtex-4 FPGAs (コンピュータシステム)
- Effective hardware task context switching in Virtex-4 FPGAs (リコンフィギャラブルシステム)
- Dielectric and Piezoelectric Properties of 0.91Pb(Zn_Nb_)O_3-0.09PbTiO_3/ Polyvinylidene Fluoride Composites Produced by the Sol-Gel Method
- LRRK2 P755L variant in sporadic Parkinson's disease
- Instruction Schecduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches (Special Section on VLSI Design and CAD Algorithms)
- Language and Compiler for Optimizing Datapath Widths of Embedded Systems (Special Section on VLSI Design and CAD Algorithms)
- Soft-Core Processor Architecture for Embedded System Design(Special Issue on Novel VLSI Processor Architectures)
- Task migration for energy savings in multiprocessor real-time systems (VLSI設計技術)
- A dynamic algorithm for energy savings in DEPS framework (組込みシステム)
- Power Management for Idle Time in the Presence of Periodic Interrupt Services
- Power Management for Idle Time in the Presence of Periodic Interrupt Services
- Power Management for Idle Time in the Presence of Periodic Interrupt Services
- Power Management for Idle Time in the Presence of Periodic Interrupt Services
- Memory Data Organization for Low-Energy Address Buses(Low-Power System LSI, IP and Related Technologies)
- ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts(System Programs)
- Impacts of Compiler Optimizations on Address Bus Energy : An Empirical Study(VLSI Design Technology and CAD)
- Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model
- An Effective GA-Based Scheduling Algorithm for FlexRay Systems
- A front-end for better behavioral synthesis
- A front-end for better behavioral synthesis
- Embedded System Cost Optimization via Data Path Width Adjustment (Special Issue on Synthesis and Verification of Hardware Design)
- Satsuki: An Integrated Processor Synthesis and Compiler Generation System (Special Issue on Synthesis and Verification of Hardware Design)
- Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
- Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
- Function Call Optimization for Efficient Behavioral Synthesis
- An RTOS-Based Design and Validation Methodology for Embedded Systems(System Programs)
- RTOS-Centric Cosimulator for Embedded System Design
- Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems
- Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
- Module Selection Using Manufacturing Information (Special Section on VLSI Design and CAD Algorithms)
- Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs : Hardware and Reconfiguration Layers
- A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs
- PLA2G6 variant in Parkinson's disease
- Comprehensive mutational analysis of LRRK2 reveals variants supporting association with autosomal dominant Parkinson's disease
- Embedded System Covalidation with RTOS Model and FPGA
- A Commentary on Axon guidance pathway genes and Parkinson's disease
- Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis