Instruction Schecduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches (Special Section on VLSI Design and CAD Algorithms)

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In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and amain memory when instuction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
社団法人電子情報通信学会の論文
1998-12-25