Embedded System Covalidation with RTOS Model and FPGA
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概要
- 論文の詳細を見る
This paper presents a software/hardware covalidation environment for embedded systems. Our covalidation environment consists of a simulation model of RTOS which fully supports services of ITRON multiple hardware simulators FPGA and a covalidation backplane. All of the simulators are executed concurrently with communication. The RTOS model can be executed on the host computer natively therefore the software can be simulated much faster than on an instruction set simulator. FPGA can execute the hardware much faster than HDL simulators. With the RTOS model and FPGA both application software and hardware can be validated in a short time. In the experiment with using our covalidation environment we perform covalidation of an MPEG4 decoder system and show the effectiveness of the covalidation environment.
- 一般社団法人情報処理学会の論文
- 2008-08-27
著者
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Shinya Honda
Graduate School of Information Science, Nagoya University
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Yuko Hara
Graduate School Of Information Science Nagoya University | Research Fellow Of The Japan Society For
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Shinya Honda
Graduate School Of Information Science Nagoya University
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Hiroaki Takada
Graduate School Of Information Science Nagoya University
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Yuko Hara
Graduate School of Information Science Nagoya University
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Hiroyuki Tomiyama
Graduate School of Information Science Nagoya University
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Seiya Shibata
Graduate School of Information Science Nagoya University
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