Shinya Honda | Graduate School Of Information Science Nagoya University

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概要

• 同名の論文著者
• Graduate School Of Information Science Nagoya Universityの論文著者

関連著者

• Shinya Honda

  Graduate School of Information Science, Nagoya University

• Shinya Honda

  Graduate School Of Information Science Nagoya University

• Hiroaki Takada

  Graduate School Of Information Science Nagoya University

• Hiroaki Takada

  Graduate School of Information Science, Nagoya University

• Hiroyuki Tomiyama

  Ritsumeikan University

• Daniel Sangorrin

  Graduate School of Information Science, Nagoya University

• Daniel Sangorrin

  Graduate School Of Information Science Nagoya University

• Seiya Shibata

  Graduate School of Information Science Nagoya University

• 高田 広章

  豊橋技科大

• Hiroaki Takada

  Nagoya University

• Yuko Hara

  Graduate School Of Information Science Nagoya University | Research Fellow Of The Japan Society For

• Takada Hiroaki

  Graduate School Of Information Science Nagoya University

• 高田 広章

  名古屋大学大学院情報科学研究科附属組込みシステム研究センター|名古屋大学大学院情報科学研究科情報システム学専攻

• Takada Hiroaki

  Nagoya Univ.

• 高田 宏章

  豊橋技術科学大学情報工学系

• 高田 広

  東京大学理学部

• 高田 広章

  名古屋大 大学院情報科学研究科 組込みシステム研究セ

• 高田 広章

  東大・理

• 高田 広章

  Nagoya University

• Takuya Azumi

  Ritsumeikan University

• Takuya Azumi

  Colleage of Information Science and Engineering, Ritsumeikan University

• Yuko Hara

  Graduate School of Information Science Nagoya University

• Hiroyuki Tomiyama

  College of Science and Engineering, Ritsumeikan University

• Hiroyuki Tomiyama

  Graduate School of Information Science Nagoya University

• Yuki Ando

  Graduate School of Information Science, Nagoya University

• 高田 広章

  豊橋技術科学大学

• Honda Shinya

  Graduate School Of Information Science Nagoya University

• 高田 広章

  名古屋大学 大学院情報科学研究科

• Hiroyuki Tomiyama

  Graduate School of Information Science, Nagoya University

• Seiya Shibata

  Graduate School of Information Science, Nagoya University|Japan Society for the Promotion of Science

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著作論文

• Integrated Scheduling in a Real-Time Embedded Hypervisor
• Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis
• Inter-OS Communications for a Real-Time Dual-OS Monitor
• Inter-OS Communications for a Real-Time Dual-OS Monitor
• HW/SW Cosimulation Framework Based on Software Component System
• HW/SW Cosimulation Framework Based on Software Component System
• Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation
• A Fast Performance Estimation Framework for System-Level Design Space Exploration
• Embedded System Covalidation with RTOS Model and FPGA

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