Takada Hiroaki | Graduate School Of Information Science Nagoya University

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概要

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著作論文

A realization of RPC in embedded component systems (システムLSI設計技術・組込みシステム・組込技術とネットワークに関するワークショップETNET2008)
Effective hardware task context switching in Virtex-4 FPGAs (VLSI設計技術)
Effective hardware task context switching in Virtex-4 FPGAs (コンピュータシステム)
Effective hardware task context switching in Virtex-4 FPGAs (リコンフィギャラブルシステム)
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation
Integrated Scheduling in a Real-Time Embedded Hypervisor
Task migration for energy savings in multiprocessor real-time systems (VLSI設計技術)
Power Management for Idle Time in the Presence of Periodic Interrupt Services
Power Management for Idle Time in the Presence of Periodic Interrupt Services
Power Management for Idle Time in the Presence of Periodic Interrupt Services
A realization of RPC in embedded component systems (コンピュータシステム・組込技術とネットワークに関するワークショップETNET2008)
A realization of RPC in embedded component systems (ディペンダブルコンピューティング・組込技術とネットワークに関するワークショップETNET2008)
Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model
An Effective GA-Based Scheduling Algorithm for FlexRay Systems
A Realization of RPC in Embedded Component Systems
Inter-OS Communications for a Real-Time Dual-OS Monitor
Inter-OS Communications for a Real-Time Dual-OS Monitor
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems
Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems
A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs
Integrated Scheduling for a Reliable Dual-OS Monitor
Integrated Scheduling for a Reliable Dual-OS Monitor
Embedded System Covalidation with RTOS Model and FPGA
Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework
Worst Case Response Time Analysis for Messages in Controller Area Network with Gateway
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis
A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs

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