A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs

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A realization of RPC in embedded component systems (システムLSI設計技術・組込みシステム・組込技術とネットワークに関するワークショップETNET2008)
Embedded System Covalidation with RTOS Model and FPGA
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Power Management for Idle Time in the Presence of Periodic Interrupt Services
Power Management for Idle Time in the Presence of Periodic Interrupt Services
Power Management for Idle Time in the Presence of Periodic Interrupt Services
Power Management for Idle Time in the Presence of Periodic Interrupt Services
A realization of RPC in embedded component systems (コンピュータシステム・組込技術とネットワークに関するワークショップETNET2008)
A realization of RPC in embedded component systems (ディペンダブルコンピューティング・組込技術とネットワークに関するワークショップETNET2008)
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Inter-OS Communications for a Real-Time Dual-OS Monitor
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
Function Call Optimization for Efficient Behavioral Synthesis
An RTOS-Based Design and Validation Methodology for Embedded Systems(System Programs)
RTOS-Centric Cosimulator for Embedded System Design
Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems
Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
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Integrated Scheduling for a Reliable Dual-OS Monitor
Integrated Scheduling for a Reliable Dual-OS Monitor
Embedded System Covalidation with RTOS Model and FPGA
Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework
A Fast Performance Estimation Framework for System-Level Design Space Exploration
Worst Case Response Time Analysis for Messages in Controller Area Network with Gateway
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis
A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs

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