A Fast Performance Estimation Framework for System-Level Design Space Exploration (System LSI Design Methodology Vol.5)

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概要

• 論文の詳細を見る

著者

• Honda Shinya

  Graduate School of Information Science, Nagoya University

• Honda Shinya

  Graduate School Of Information Science Nagoya University

• Ando Yuki

  Graduate School Of Information Science Nagoya University

• Shibata Seiya

  Graduate School Of Information Science Nagoya University

関連論文

• Embedded System Covalidation with RTOS Model and FPGA
• Effective hardware task context switching in Virtex-4 FPGAs (VLSI設計技術)
• Effective hardware task context switching in Virtex-4 FPGAs (コンピュータシステム)
• Effective hardware task context switching in Virtex-4 FPGAs (リコンフィギャラブルシステム)
• Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation
• Integrated Scheduling in a Real-Time Embedded Hypervisor
• Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
• Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
• Function Call Optimization for Efficient Behavioral Synthesis
• An RTOS-Based Design and Validation Methodology for Embedded Systems(System Programs)
• RTOS-Centric Cosimulator for Embedded System Design
• Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
• Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs : Hardware and Reconfiguration Layers
• A Fast Performance Estimation Framework for System-Level Design Space Exploration (System LSI Design Methodology Vol.5)
• A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs
• Integrated Scheduling for a Reliable Dual-OS Monitor
• Integrated Scheduling for a Reliable Dual-OS Monitor
• Embedded System Covalidation with RTOS Model and FPGA
• A Fast Performance Estimation Framework for System-Level Design Space Exploration
• Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis
• A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
• A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
• A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs

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