An RTOS-Based Design and Validation Methodology for Embedded Systems(System Programs)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper presents an RTOS-based methodology for design and validation of embedded systems. The heart of our methodology is the use of an RTOS simulation model from the very early stage of the system design. A case study with a JPEG decoder application is also presented in order to demonstrate the effectiveness of our methodology.

• 社団法人電子情報通信学会の論文
• 2005-09-01

著者

• Honda Shinya

  Graduate School of Information Science, Nagoya University

• Shinya Honda

  Graduate School of Information Science, Nagoya University

• TOMIYAMA Hiroyuki

  Department of Pblymer Science and Engineering, Faculty of Engineering, Yamagata University

• HONDA Shinya

  Department of Neurosurgery, Kochi Medical School

• Honda Shinya

  Graduate School Of Information Science Nagoya University

• Honda Shinya

  Department Of Biological Science And Technology And Tissue Engineering Research Center Tokyo Univers

• Takada Hiroaki

  Department Of Electrical Engineering Chiba University

• Tomiyama Hiroyuki

  Graduate School Of Information Science Nagoya University

• Tomiyama Hiroyuki

  The Department Of Computer Science And Communication Engineering Graduate School Of Information Scie

• Tomiyama Hiroyuki

  The Interdisciplinary Graduate School Of Engineering Sciences Kyushu University

• Tomiyama Hiroyuki

  Department Of Neurology Juntendo University School Of Medicine

• Takada H

  Graduate School Of Information Science Nagoya University

• Tomiyama H

  Department Of Information Engineering The Graduate School Of Information Science Nagoya University

• Takada H

  Department Of Information Engineering The Graduate School Of Information Science Nagoya University

• Tomiyama H

  Graduate School Of Information Science Nagoya University

• CHIKADA Shin-ichiro

  Department of Information Engineering, the Graduate School of Information Science, Nagoya University

• Tomiyama Hiroyuki

  Department Of Information Engineering The Graduate School Of Information Science Nagoya University

• Chikada Shin-ichiro

  Department Of Information Engineering The Graduate School Of Information Science Nagoya University

関連論文

• Embedded System Covalidation with RTOS Model and FPGA
• Integrated Scheduling in a Real-Time Embedded Hypervisor
• Effective hardware task context switching in Virtex-4 FPGAs (VLSI設計技術)
• Effective hardware task context switching in Virtex-4 FPGAs (コンピュータシステム)
• Effective hardware task context switching in Virtex-4 FPGAs (リコンフィギャラブルシステム)
• Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation
• Dielectric and Piezoelectric Properties of 0.91Pb(Zn_Nb_)O_3-0.09PbTiO_3/ Polyvinylidene Fluoride Composites Produced by the Sol-Gel Method
• Successful Percutaneous Transluminal Angioplasty of the Intracranial Vertebral Artery 1 Month after Total Occlusion : Case Report
• Percutaneous Transluminal Angioplasty of Supra-aortic Arterial Stenoses in Patients with Concomitant Cerebrovascular and Coronary Artery Diseases : Report of Two Cases
• Carrier Transport in Polycrystalline Silicon Thin Film Solar Cells Grown on a Highly Textured Structure
• Carrier Transport in Polycrystalline Silicon Photovoltaic Layer on Highly Textured Substrate
• LRRK2 P755L variant in sporadic Parkinson's disease
• Integrated Scheduling in a Real-Time Embedded Hypervisor
• Instruction Schecduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches (Special Section on VLSI Design and CAD Algorithms)
• Language and Compiler for Optimizing Datapath Widths of Embedded Systems (Special Section on VLSI Design and CAD Algorithms)
• Soft-Core Processor Architecture for Embedded System Design(Special Issue on Novel VLSI Processor Architectures)
• Task migration for energy savings in multiprocessor real-time systems (VLSI設計技術)
• A dynamic algorithm for energy savings in DEPS framework (組込みシステム)
• Power Management for Idle Time in the Presence of Periodic Interrupt Services
• Power Management for Idle Time in the Presence of Periodic Interrupt Services
• Power Management for Idle Time in the Presence of Periodic Interrupt Services
• Power Management for Idle Time in the Presence of Periodic Interrupt Services
• Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis
• Memory Data Organization for Low-Energy Address Buses(Low-Power System LSI, IP and Related Technologies)
• ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts(System Programs)
• Migration and differentiation of neural cell lines transplanted into mouse brains
• Impacts of Compiler Optimizations on Address Bus Energy : An Empirical Study(VLSI Design Technology and CAD)
• Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model
• An Effective GA-Based Scheduling Algorithm for FlexRay Systems
• A front-end for better behavioral synthesis
• A front-end for better behavioral synthesis
• Propagation Characteriristics of SAW on ZnO/AIN/GaAs-Substrate Structure : SAW and Communication Devices
• Inter-OS Communications for a Real-Time Dual-OS Monitor
• Inter-OS Communications for a Real-Time Dual-OS Monitor
• Prenatal Diagnosis of Intrapericardial Teratoma : A Case Report
• HW/SW Cosimulation Framework Based on Software Component System
• HW/SW Cosimulation Framework Based on Software Component System
• Embedded System Cost Optimization via Data Path Width Adjustment (Special Issue on Synthesis and Verification of Hardware Design)
• Satsuki: An Integrated Processor Synthesis and Compiler Generation System (Special Issue on Synthesis and Verification of Hardware Design)
• Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
• Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
• Function Call Optimization for Efficient Behavioral Synthesis
• An RTOS-Based Design and Validation Methodology for Embedded Systems(System Programs)
• RTOS-Centric Cosimulator for Embedded System Design
• Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems
• Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
• Module Selection Using Manufacturing Information (Special Section on VLSI Design and CAD Algorithms)
• Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs : Hardware and Reconfiguration Layers
• A Fast Performance Estimation Framework for System-Level Design Space Exploration (System LSI Design Methodology Vol.5)
• A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs
• PLA2G6 variant in Parkinson's disease
• Comprehensive mutational analysis of LRRK2 reveals variants supporting association with autosomal dominant Parkinson's disease
• Integrated Scheduling for a Reliable Dual-OS Monitor
• Integrated Scheduling for a Reliable Dual-OS Monitor
• Embedded System Covalidation with RTOS Model and FPGA
• Carrier Transport in Polycrystalline Silicon Thin Film Solar Cells Grown on a Highly Textured Structure
• Carrier Transport in Polycrystalline Silicon Photovoltaic Layer on Highly Textured Substrate
• Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation
• A Fast Performance Estimation Framework for System-Level Design Space Exploration
• Embedded System Covalidation with RTOS Model and FPGA
• A Commentary on Axon guidance pathway genes and Parkinson's disease
• Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis
• Individuality of amino acid residues in protected peptides. Conformational and .BETA.-sheet structure-disrupted behaviors of resin-bound peptides.
• A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
• A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
• Infrared absorption study of human proinsulin C-peptide fragments in dichloromethane.
• The electron donor-acceptor interaction between mixed solvents and its influence on their .BETA.-sheet strucutre-disrupting potential.
• The .BETA.-sheet structure-disrupting potential of electron-donor and -acceptor solvents and role of mixed solvents in solvation of peptides.
• The solubility of peptide intermediates in organic solvents. Solubilizing potential of hexafluoro-2-propanol.
• A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
• Infrared absorption study of human proinsulin C-peptide fragments in the solid state.
• The study on peptide and protein syntheses. Infrared spectroscopic conformational analysis of oligo-L-leucines containing only one D-amino acid residue.

もっと見る 閉じる

スポンサーリンク