Memory Data Organization for Low-Energy Address Buses(<Special Section>Low-Power System LSI, IP and Related Technologies)
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概要
- 論文の詳細を見る
Energy consumption has become one of the most critical constraints in the design of portable multimedia systems. For media applications, address buses between processor and data memory consume a considerable amount of energy due to their large capacitance and frequent accesses. This paper studies impacts of memory data organization on the address bus energy. Our experiments show that the address bus activity is significantly reduced by 50% through exploring memory data organization and encoding address buses.
- 社団法人電子情報通信学会の論文
- 2004-04-01
著者
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TOMIYAMA Hiroyuki
Department of Pblymer Science and Engineering, Faculty of Engineering, Yamagata University
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Takada Hiroaki
Department Of Electrical Engineering Chiba University
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Tomiyama Hiroyuki
Graduate School Of Information Science Nagoya University
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Tomiyama Hiroyuki
The Department Of Computer Science And Communication Engineering Graduate School Of Information Scie
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Tomiyama Hiroyuki
The Interdisciplinary Graduate School Of Engineering Sciences Kyushu University
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Dutt Nikil
Center Of Embedded Computer Systems University Of California
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Dutt Nikil
Center For Embedded Computer Systems University Of California
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Dutt Nikil
Faculty Of Information And Computer Science Uc-irvine
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Dutt Nikil
Department Of Information And Computer Science University Of California
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Tomiyama H
Department Of Information Engineering The Graduate School Of Information Science Nagoya University
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Takada H
Department Of Information Engineering The Graduate School Of Information Science Nagoya University
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Takada Hiroaki
Department Of Information Engineering The Graduate School Of Information Science Nagoya University
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Tomiyama Hiroyuki
Department Of Information Engineering The Graduate School Of Information Science Nagoya University
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TOMIYAMA Hiroyuki
Center of Embedded Computer Systems, University of California
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