High-Level Synthesis with SDRAMs and RAMBUS DRAMs (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
Newer off-chip DRAM families, including Synchronous DRAMs (SDRAMs) and RAMBUS DRAMs (RDRAMs), are becoming standard choices for the design of high-performance systems. Although previous work in High-Level Synthesis (HLS) has addressed exploiting features of pagemode DRAMs, techniques do not exist for exploiting the two key features of these newer DRAM families that boost memory performance and help overcome bandwidth limitations: (1) burst mode access, and (2) interleaved access through multiple banks. We address pre-synthesis optimizations on the input behavior that extract and exploit the burst mode and multiple bank interleaved access modes of these newer DRAM families, so that these features can be exploited fully during the HLS trajectory. Our experiments, run on a suite of memory-intensive benchmarks using a contemporary SDRAM library, demonstrate significant performance improvements of up to 62.5% over the naive approach, and improvements of up to 16.7% over the previous approach that considered only page-modeor extended-data-out (EDO) DRAMS.
- 社団法人電子情報通信学会の論文
- 1999-11-25
著者
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Dutt Nikil
Faculty Of Information And Computer Science Uc-irvine
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KHARE Asheesh
ICS Department at UC-Irvine
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PANDA Preeti
Synopsys, Inc., Mountain View
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NICOLAU Alexandru
Faculty of Information and Computer Science, UC-Irvine
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Panda Preeti
Synopsys Inc. Mountain View
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Nicolau Alexandru
Faculty Of Information And Computer Science Uc-irvine
関連論文
- High-Level Synthesis with SDRAMs and RAMBUS DRAMs (Special Section on VLSI Design and CAD Algorithms)
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