Analytic Modeling for Drain-Induced Barrier Lowering Phenomenon of the InGaP/InGaAs/GaAs Pseudomorphic Doped-Channel Field-Effect Transistor

概要

論文の詳細を見る
A two-dimensional analytic model for characterizing the drain-induced barrier lowering (DLBL) phenomenon for the InGaP/lnGaAs/GaAs pseudomorphic doped-channel field-effect transistor (PDCFET) is proposed. By solving nonlinear equations with the Newton method, this model provides a straightforward physical expression of the channel potential profile near or within the sub-threshold regime for short-channel effects. Calculations for a specified PDCFET device structure with a gate length of 0.25 μm have been conducted and results demonstrated that the pinch-off channel, at a gate-to-source bias of 1.2 V, will resume current conduction as the potential barrier is lowered comparably to the thermal voltage when the drain bias elevates to 2.2 V. This work presents a comprehensive investigation, and fast and convenient estimation for the short-channel effect, and can be extended to multichannel PDCFET structures.
社団法人応用物理学会の論文
2002-10-15