Impacts of Surface Roughness Reduction in (110) Si Substrates Fabricated by High-Temperature Annealing on Electron Mobility in n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors on (110) Si (Special Issue : Solid State Devices and Materials)

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概要

• 論文の詳細を見る
• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文

著者

• MATSUMOTO Hiroaki

  Hitachi High-Tech Manufacturing and Service Corporation

• Takenaka Mitsuru

  Department Of Electrical Engineering And Information Systems School Of Engineering The University Of

• Takagi Shinichi

  Department Of Electrical Engineering And Information Systems The University Of Tokyo

• Izunome Koji

  Covalent Materials Corporation, 6-861-5 Higashi-ko, Seiro, Kitakanbara, Niigata 957-0197, Japan

• Taoka Noriyuki

  Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan

• Jeon Sung-Ho

  Department of Electrical Engineering and Information Systems, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan

• Araki Koji

  Covalent Silicon Corporation, Seiro, Niigata 957-0197, Japan

• Nakano Kiyotaka

  Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan

• Koyama Susumu

  Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan

• Kakibayasi Hiroshi

  Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan

• Miyashita Moriya

  Covalent Silicon Corporation, Seiro, Niigata 957-0197, Japan

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• Impacts of Surface Roughness Reduction in (110) Si Substrates Fabricated by High-Temperature Annealing on Electron Mobility in n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors on (110) Si (Special Issue : Solid State Devices and Materials)

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