Impacts of Surface Roughness Reduction in (110) Si Substrates Fabricated by High-Temperature Annealing on Electron Mobility in n-Channel Metal--Oxide--Semiconductor Field-Effect Transistors on (110) Si

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概要

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• The effects of high-temperature Ar/H<inf>2</inf>annealing on (110) Si, which is known to provide flat (110) Si surfaces, have been studied from the viewpoint of metal--oxide--semiconductor (MOS) interface roughness and inversion-layer electron mobility limited by surface roughness scattering in (110) Si n-channel metal--oxide--semiconductor field-effect transistors (n-MOSFETs). It has been confirmed by quantitative transmission electron microscope (TEM) analysis that the reduction in the surface roughness on (110) Si is still maintained after gate oxidation with gate oxide thickness (T_{\text{ox}}) of 6.9 nm. The mobility measurement of (110) Si n-MOSFETs fabricated using Si wafers with high-temperature Ar/H<inf>2</inf>annealing has revealed that the high-temperature annealing increases the electron mobility of (110) Si MOSFETs at 10 K by 14 and 5.7% for T_{\text{ox}} values of 6.9 and 8.9 nm, respectively, and increases the electron mobility at 300 K by 2.5 and 0.72% for T_{\text{ox}} values of 6.9 and 8.9 nm, respectively. The T_{\text{ox}} dependence of the enhancement factor might be attributable to the increase in MOS interface roughness with increasing T_{\text{ox}}. It has also been observed that the mobility enhancement factor is slightly dependent on the channel direction. The mobility increase has been observed to be greater along \langle 111\rangle than along \langle 112\rangle.

• 2013-04-25

著者

• MATSUMOTO Hiroaki

  Hitachi High-Tech Manufacturing and Service Corporation

• Takenaka Mitsuru

  Department Of Electrical Engineering And Information Systems School Of Engineering The University Of

• Takagi Shinichi

  Department Of Electrical Engineering And Information Systems The University Of Tokyo

• Izunome Koji

  Covalent Materials Corporation, 6-861-5 Higashi-ko, Seiro, Kitakanbara, Niigata 957-0197, Japan

• Taoka Noriyuki

  Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan

• Jeon Sung-Ho

  Department of Electrical Engineering and Information Systems, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan

• Taoka Noriyuki

  Department of Electrical Engineering and Information Systems, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan

• Araki Koji

  Covalent Silicon Corporation, Seiro, Niigata 957-0197, Japan

• Nakano Kiyotaka

  Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan

• Koyama Susumu

  Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan

• Kakibayasi Hiroshi

  Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan

• Miyashita Moriya

  Covalent Silicon Corporation, Seiro, Niigata 957-0197, Japan

• Matsumoto Hiroaki

  Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan

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