Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal--Oxide--Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO2 Interfacial Layers

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概要

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• We have successfully fabricated high hole mobility Ge p-channel metal--oxide--semiconductor field-effect transistors (p-MOSFETs) with GeO2/Ge formed by direct thermal oxidation, which can yield a significantly low interface trap density ($D_{\text{it}}$). Al2O3 films are employed as capping layers for protecting the GeO2/Ge MOS interfaces during the MOSFET fabrication processes. The source/drain (S/D) regions are formed by boron ion implantation in a self-align way with Al gate metal. The good MOS interface properties are found to be maintained even after the activation annealing at temperatures sufficient for obtaining the excellent junction properties. The fabricated MOSFETs exhibit high source and drain on/off current ratios of $10^{5}$--$10^{4}$ and a high peak hole mobility of 575 cm2 V-1 s-1 at maximum, both of which are attributable to the excellent GeO2/Ge MOS interface properties. The effects of the substrate impurity concentration and the thickness of GeO2 on the hole mobility are examined. It is found from the results for different substrate impurity concentrations that the universal curve between hole mobility and the effective field $E_{\text{eff}}$ holds for $\eta = 1/3$. We also investigate the impact of the oxidation temperature dependence on hole mobility in order to examine the scattering mechanism limiting the mobility of GeO2/Ge interfaces through the modulation of the MOS interfaces by changing oxidation temperature. It is found that the mobility in low-temperature and low-surface carrier density ($N_{\text{s}}$) regions is well corrected with $D_{\text{it}}$ evaluated from S factors in MOSFETs. In addition, it is revealed from transmission electron microscopy analyses that the interface roughness between GeO2 and Ge is reduced with increasing oxidation temperature. From these experimental results, the higher mobility of GeO2/Ge p-MOSFET at higher oxidation temperatures can be explained by the reduction in the density of Coulomb scattering centers and surface roughness at elevated Ge oxidation temperatures.

• 2011-01-25

著者

• Nakane Ryosho

  Department Of Electrical Engineering And Information Systems The University Of Tokyo

• Takenaka Mitsuru

  Department Of Electrical Engineering And Information Systems School Of Engineering The University Of

• Takagi Shinichi

  Department Of Electrical Engineering And Information Systems The University Of Tokyo

• Nakakita Yosuke

  Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Tokyo 113-8656, Japan

• Sasada Takashi

  Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Tokyo 113-8656, Japan

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