Simulation and Fabrication of InGaP/Al0.98Ga0.02As/GaAs Oxide-Confined Collector-Up Heterojunction Bipolar Transistors

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概要

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• Two-dimensional numerical simulations were performed to investigate the proposed oxide-confined collector-up heterojunction bipolar transistors (C-up HBTs). To achieve a high current gain, the effective base-emitter junction area should be decreased to be smaller than that of the base-collector junction. However, at the same time the offset voltage was increased by the decrease of the base-emitter junction area. A trade-off between the current gain and the offset voltage was observed for C-up HBTs. In the device fabrication, the current confinement of the partially oxidized Al0.98Ga0.02As layer was demonstrated by a simple current–voltage measurement applied to the base-emitter junction. With applying a 400°C oxidation process for 70 min, a current gain of 79 can be achieved with a low base sheet resistance of 203 $\Omega$/sq. and an offset voltage of 160 mV. The relationship between the current gain and the offset voltage obtained from the experimental results shows the same trend as that observed in the simulations. The optimized condition of the oxidation depth is that in which the effective base-emitter junction area is slightly smaller than that of the base-collector junction.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2004-08-15

著者

• Chen Shi-ming

  Epitech Technology Corporation

• Chen Wen-bin

  Department Of Electrical Engineering And Institute Of Microelectronics National Cheng Kung Universit

• Su Yan-kuin

  Department Of Electrical Engineering And Institute Of Microelectronics National Cheng Kung Universit

• SU Juh-Yuh

  Epitech Technology Corporation

• Yu Hsin-chieh

  Department Of Electrical Engineering And Institute Of Microelectronics National Cheng Kung Universit

• Wang Hsin-chuan

  Department Of Electrical Engineering And Institute Of Microelectronics National Cheng Kung Universit

• Lin Chun-liang

  Department Of Advanced Materials Science Graduate School Of Frontier Science University Of Tokyo

• Chen Wen-Bin

  Department of Electrical Engineering and Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan, Taiwan 70101, R.O.C.

• Lin Chun-Liang

  Department of Electrical Engineering and Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan, Taiwan 70101, R.O.C.

• Chen Shi-Ming

  Epitech Technology Corporation, No. 10 Da-Shuen 9th Rd., Tainan Science-Based Industrial Park, Tainan, Taiwan 74145, R.O.C.

• Su Yan-Kuin

  Department of Electrical Engineering and Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan, Taiwan 70101, R.O.C.

• Yu Hsin-Chieh

  Department of Electrical Engineering and Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan, Taiwan 70101, R.O.C.

• Wang Hsin-Chuan

  Department of Electrical Engineering and Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan, Taiwan 70101, R.O.C.

• Su Juh-Yuh

  Epitech Technology Corporation, No. 10 Da-Shuen 9th Rd., Tainan Science-Based Industrial Park, Tainan, Taiwan 74145, R.O.C.

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