Strained Silicon–Germanium-on-Insulator n-Channel Transistor with Silicon Source and Drain Regions for Performance Enhancement

概要

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We report the incorporation of lattice-mismatched source/drain (S/D) stressors for the formation of strained SiGe n-channel transistors with gate lengths $L_{\text{G}}$ down to 70 nm. The strained SiGe channel transistor features silicon S/D regions which are pseudomorphically grown by selective epitaxy. Lattice mismatch between the silicon S/D region and the SiGe channel was exploited to induce lateral tensile strain and vertical compressive strain in the channel, leading to enhancement in electron mobility. Experimental results on the strained SiGe n-channel transistors correlate well with stress simulations. Control devices with the lattice-matched SiGe S/D were also fabricated. At a gate length of 70 nm, the tensile strained-SiGe channel n-FET with Si S/D demonstrates 36% higher linear drain current and 20% higher saturation drive current over the control device.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2007-04-30