Concept of Strain-Transfer-Layer and Integration with Graded Silicon–Germanium Source/Drain Stressors for p-Type Field Effect Transistor Performance Enhancement

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概要

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• We report a novel strained Si0.75Ge0.25 channel p-type field effect transistor (p-FET) that employs a silicon strain-transfer-layer (STL) buried beneath the channel. At the vertical heterojunction, the compliant silicon strain-transfer-layer, improves the coupling of lattice interactions between the lattice-mismatched SiGe source/drain (S/D) stressors and the channel region. In addition, the lattice interaction between the adjacent S/D stressors and the Si0.75Ge0.25 channel induces, yet another source of compressive strain in the channel region. A large lateral compressive strain is obtained in the Si0.75Ge0.25 channel region for hole mobility enhancement. Devices with gate length $L_{\text{G}}$ down to 50 nm were fabricated. The strain effects resulted in 84% drive current improvement over unstrained Si channel devices.

• 2008-04-25

著者

• Yeo Yee-chia

  Silicon Nano Device Lab (sndl) Ece Department National University Of Singapore

• TUNG Chih-Hang

  Institute of Microelectronics

• Samudra Ganesh

  Silicon Nano Device Lab Dept. Of Ece National University Of Singapore (nus)

• Toh Eng-huat

  Silicon Nano Device Lab. Dept. Of Electrical And Computer Engineering National University Of Singapo

• Yeo Yee-Chia

  Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576

• Tripathy Sudhinranjan

  Institute of Materials Research and Engineering, 3 Research Link, Singapore 117602

• Wang Grace

  Silicon Nano Device Lab, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576

• Wang Grace

  Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576

• Toh Eng-Huat

  Silicon Nano Device Lab, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576

• Toh Eng-Huat

  Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576

• Samudra Ganesh

  Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576

• Tung Chih-Hang

  Institute of Microelectronics, 11 Science Park Road, Singapore 117685

関連論文

• Silicon Strain-Transfer-Layer (STL) and Graded Source/Drain Stressors for Enhancing the Performance of Silicon-Germanium Channel P-MOSFETs
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