システムLSI の低消費電力化, 高密度化の現状と将来展望

概要

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Low-power design of system LSI in the presence of leakage current has been described. And also the novel designtechnique for realizing high density system LSI featured by the 3-dimensional transistor has been presented. By usingparallel processing architecture the active power of embedded processor with the sub-threshold leakage current can bereduced to 1/2 for 2 parallel, 1/5 for 3 parallel case. The dual-supply voltage scheme enables to reduce the active power ofembedded processor with the gate leakage current to 35–50%. By using FinFET the pattern area of system LSI can bereduced to 35–50% without sacrificing the performance. These technologies are promising candidates for realizing thebreakthrough the 3-limitation of system LSI, power dissipation, scaling of MOS transistor and time to market of systemLSI.
湘南工科大学の論文
2007-03-18