Performance Improvement of Polycrystalline Silicon Nanowire Thin-Film Transistors by a High-$k$ Capping Layer
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概要
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In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-$k$ material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-$k$ passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2009-02-25
著者
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Huang Tiao-yuan
Department Of Electronics Engineering & Institute Of Electronics National Chiao Tung University
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Lin Horng-chih
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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Lee Ko-Hui
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan 300, R.O.C.
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Huang Tiao-Yuan
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan 300, R.O.C.
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Hsu Hsing-Hui
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan 300, R.O.C.
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Lin Horng-Chih
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan 300, R.O.C.
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