Investigations of an Independent Double-Gated Polycrystalline Silicon Nanowire Thin Film Transistor for Nonvolatile Memory Operations
スポンサーリンク
概要
- 論文の詳細を見る
In this study, we investigate the merits of an independent double-gated configuration for nonvolatile memory operations. In contrast to the convention where the programming/erasing gate also acts as the read gate, a dedicated read gate with an oxide-only dielectric is proposed in the new mode. Using the same device under identical programming/erasing conditions, greatly improved programming speed (e.g., 61% increase under the stress condition of 18 V for 10 μs) is achieved, while the erasing speed, albeit initially retarded, shows enhancement when the erasing time is larger than a certain value, which can be explained by the back-gate bias effects. Retention characterization indicates that the new mode offers a larger memory window after 10 year extrapolation. In addition, a proper auxiliary gate bias applied during programming/erasing processes is found to improve the programming/erasing speed. Finally, by taking advantage of the separate-gated feature, two independent storage sites can be obtained by employing an oxide--nitride--oxide layer as the dielectric for both gates, thus realizing 2-bit/cell functionality.
- 2011-08-25
著者
-
Huang Tiao-yuan
Department Of Electronics Engineering & Institute Of Electronics National Chiao Tung University
-
Lin Horng-chih
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
-
Chen Wei-chen
Department Of Chemistry National Tsing Hua University
-
Huang Tiao-Yuan
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 300, R.O.C.
-
Chen Wei-Chen
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 300, R.O.C.
-
Lin Horng-Chih
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 300, R.O.C.
関連論文
- A New Method to Extract MOSFET Threshold Voltage, Effective Channel Length, and Channel Mobility Using S-parameter Measurement(Active Devices and Circuits)(Advances in Characterization and Measurement Technologies for Microwave and Millim
- Characteristics of Poly-Si Nanowire Thin Film Transistors with Double-Gated Structures
- Hot Carrier Degradations of Dynamic Threshold Silicon on Insulator p-Type Metal-Oxide-Semiconductor Field Effect Transistors
- Impacts of LP-SiN Capping Layer and Lateral Diffusion of interface Trap on Hot Carrier Stress of NMOSFETs
- A novel method to convert metallic-type CNTs to semiconducting-type CNT-FETs
- Application of Field-Induced Source/Drain Schottky Metal-Oxide-Semiconductor to Fin-Like Body Field-Effect Transistor : semiconductors
- Impact of Thermal Stability on the Characteristics of Complementary Metal Oxide Semiconductor Transistors with TiN Metal Gate
- Plasma-Process-Induced Damage in Sputtered TiN Metal-Gate Capacitors with Ultrathin Nitrided Oxides
- The Combined Effects of Nitrogen Implantation at S/D Extension and N_2O Oxide on 0.18μm N- and P-Metal Oxide Field Effect Transistors (MOSEETs)
- The Effects of Shallow Germanium Halo Doping on N-Channel Metal Oxide Semiconductor Field Effect Transistors
- A Radiation-Hard Flash Cell Using Horn-Shaped Floating Gate and N_2O Annealing
- A Study on the Radiation Hardness of Flash Cell with Horn-Shaped Floating-Gate
- Effects of Floating-Gate Doping Concentration of Flash Cell Performance
- The Role of a Resist During O_2 Plasma Ashing and Its Impact on the Reliability Evaluation of Ultrathin Gate Oxides
- Fragilide A, a Novel Diterpenoid from Junceella fragilis
- Characterization of Polycrystalline Silicon Thin Film Transistors Fabricated by Ultrahigh-Vacuum Chemical Vapor Deposition and Chemical Mechanical Polishing
- Interfacial Abruptness in Si/SiGe Heteroepitaxy Grown by Ultrahigh Vacuum Chemical Vapor Deposition
- Comparison of N_2 and NH_3 Plasma Passivation Effects on Polycrystalline Silicon Thin-Film Transistors
- Devices Characteristics and Aggravated Negative Bias Temperature Instability in PMOSFETs with Uniaxial Compressive Strain
- Effects of Fluorine Incorporation on the Negative-Bias-Temperature Instability (NBTI) of P-Channel MOSFETs
- Effects of Fluorine Incorporation on the Negative-Bias-Temperature Instability (NBTI) of P-Channel MOSFETs
- Enhanced Negative-Bias-Temperature Instability of P-Channel Metal-Oxide-Semiconductor Transistors due to Plasma Charging Damage
- Post-Soft-Breakdown Characteristics of Deep Sub-Micron NMOSFETs with Ultra-Thin Gate Oxide
- Enhanced Negative-Bias-Temperature Instability of P-Channel MOSFET by Plasma Charging Damage
- Poly-Si Nanowire Thin-Film Transistors with Inverse-T Gate
- Theoretical Study on the Substrate Binding of 4-Nitrophenol : Spectral Shift, Solvent Effect and Hydrogen Bond
- Investigations of an Independent Double-Gated Polycrystalline Silicon Nanowire Thin Film Transistor for Nonvolatile Memory Operations
- Hot Carrier Degradations of Dynamic Threshold Silicon on Insulator p-Type Metal–Oxide–Semiconductor Field Effect Transistors
- The Effects of Dielectric Type and Thickness on the Characteristics of Dynamic Threshold Metal Oxide Semiconductor Transistors
- Impacts of Low-Pressure Chemical Vapor Deposition-SiN Capping Layer and Lateral Distribution of Interface Traps on Hot-Carrier Stress of n-Channel Metal–Oxide–Semiconductor Field-Effect-Transistors
- Analytical Model of Subthreshold Current and Threshold Voltage for Fully Depleted Double-Gated Junctionless Transistor
- Performance Improvement of Polycrystalline Silicon Nanowire Thin-Film Transistors by a High-$k$ Capping Layer
- Crystal Orientation and Nitrogen Effects on the Carrier Mobility of p-Type Metal Oxide Semiconductor Field Effect Transistor with Ultra Thin Gate Dielectrics
- Device Characteristics and Aggravated Negative Bias Temperature Instability in $ p$-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Uniaxial Compressive Strain
- A New Methodology for Probing the Electrical Properties of Heavily Phosphorous-Doped Polycrystalline Silicon Nanowires