High Ruggedness Power MOSFET Design by a Self-Align P+ Process(Session A7 High Power Devices)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
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概要
- 論文の詳細を見る
A noble high ruggedness Power MOSFET structure with a planar oxide deep P+ implant structure has been proposed and discussed. The conventional P+ MASK process and contact P+ implant process are used to compare with this self-align process. It is shown that the self align implant structure with a wide P+ area can reduce the parasitic BJT effect, and therefore, improve the device's avalanche energy capability, which is required for inductive load circuits.
- 社団法人電子情報通信学会の論文
- 2004-06-24
著者
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Cheng Ching
R&d Dept. Chino-excel Technology Corp.
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LAI Ming-Hung
R&D Dept., Chino-Excel Technology Crop.
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SU Shih-Tzung
R&D Dept., Chino-Excel Technology Crop.
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CHENG Ching-Ling
R&D Dept., Chino-Excel Technology Crop.
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SU Shin-Tzung
R&D Dept., Chino-Excel Technology Corp.
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TU Kou-Way
R&D Dept., Chino-Excel Technology Corp.
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Chien Feng-Tso
R&D Dept. Chino-Excel Technology Corp.
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Lai Ming
R&d Dept. Chino-excel Technology Corp.
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Tu Kou
R&d Dept. Chino-excel Technology Corp.
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Chien Feng‐tso
Dep. Of Electronic Engineering Feng Chia University
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Su Shih
R&d Dept. Chino-excel Technology Corp.
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Chien Feng-tso
The R&d Dept. Chino-excel Technology Corp.:the Department Of Electrical Engineering Feng Chia Un
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Fang Chin-mu
Department Of Electronic Engineering Feng-chia University
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Fang Chin-mu
Dept. Of Electronic Engineering Feng-chia University
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