The Study of Drain Alloy Time and Temperature for Antimony Substrate Vertical High Voltage Power MOSFETs(Session 6B Power Devices,AWAD2006)

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概要

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• Low voltage vertical Power MOSFETs employ the substrates doped by Arsenic (As) for low on-resistance issue. However, those substrates lead to un-uniformity breakdown problem for high voltage (HV) epitaxy (low concentration) caused by the out-doping phenomenon under processing. In this study, we use the antimony-doped (Sb) substrate to avoid this drawback for HV devices. However, devices fabricated with Sb-doped substrate show a higher source-drain turn on voltage (V_<SD>) owing to a higher drain contact resistance, which increase power loss than the As doped devices under device switching. To lower the V_<SD>, we bake the devices with different temperature and time conditions and investigate the V_<SD> characteristics. It is shown that the V_<SD> can be reduced 35% at 350℃ with 6 hours conditions.

• 社団法人電子情報通信学会の論文
• 2006-06-26

著者

• Wang Chi

  Dept. Of Electronic Engineering Feng Chia University

• Liao Chien

  Dep. Of Electrical Engineering National Central University

• LIAO Chien-Nan

  Dept. of Electrical Engineering, National Central University

• CHIEN Feng-Tso

  Dept. of Electronic Engineering, Feng Chia University

• WANG Chi-Ling

  Dept. of Electronic Engineering, Feng Chia University

• Chien Feng‐tso

  Dep. Of Electronic Engineering Feng Chia University

• Chien Feng-tsun

  Dept. Of Electronics Engineering National Chiao Tung University

• Chien Feng-tso

  The R&d Dept. Chino-excel Technology Corp.:the Department Of Electrical Engineering Feng Chia Un

• Liao Chien-nan

  Dept. Of Electrical Engineering National Central University

• Liao Chien-nan

  Department Of Electrical Engineering National Central University

• Fang Chin-mu

  Department Of Electronic Engineering Feng-chia University

• Fang Chin-mu

  Dept. Of Electronic Engineering Feng-chia University

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