High Ruggedness Power MOSFET Design by a Self-Align p^+ Process(Power Devices, <Special Section>Fundamental and Application of Advanced Semiconductor Devices)
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概要
- 論文の詳細を見る
A new high ruggedness Power MOSFET structure with a planar oxide self align p^+ implant structure is proposed and discussed. We compare the proposed self-align process with the conventional p^+ MASK process and contact p^+ implant process. It is shown that the self align implant structure with a wide p^+ area can reduce the parasitic BJT effect and, therefore, improve the device's avalanche energy capability, which is required for inductive load circuits. Based on the unclamped inductive load switching measurement results, the proposed device avalanche energy with self align p^+ implant process is improved about 355% as compared to the traditional one.
- 社団法人電子情報通信学会の論文
- 2005-04-01
著者
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Chien Feng
Dept. of Electronics Engineering, National Chiao Tung University
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Cheng Ching
R&d Dept. Chino-excel Technology Corp.
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LAI Ming
R&D Dept., Chino-Excel Technology Corp.
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SU Shih
R&D Dept., Chino-Excel Technology Corp.
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TU Kou
R&D Dept., Chino-Excel Technology Corp.
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CHENG Ching
R&D Dept., Chino-Excel Technology Corp.
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Lai Ming
R&d Dept. Chino-excel Technology Corp.
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Tu Kou
R&d Dept. Chino-excel Technology Corp.
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Chien Feng‐tso
Dep. Of Electronic Engineering Feng Chia University
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Su Shih
R&d Dept. Chino-excel Technology Corp.
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Chien Feng-tso
The R&d Dept. Chino-excel Technology Corp.:the Department Of Electrical Engineering Feng Chia Un
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Fang Chin-mu
Department Of Electronic Engineering Feng-chia University
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Fang Chin-mu
Dept. Of Electronic Engineering Feng-chia University
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Chien Feng
Dept. Of Electronic Engineering Feng-chia University
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