High Current, High Power, and High Linearity Ohmic Recess InGaP/InGaAs Doped Channel FETs(Session 7B Compound Semiconductor Devices III,AWAD2006)
スポンサーリンク
概要
- 論文の詳細を見る
Performance of contact resistance, dc, rf, microwave power, and device linearity characteristics between proposed partial drain/source ohmic recess InGaP/InGaAs/GaAs doped-channel FETs (OR-DCFETs) and the conventional doped-channel FETs (DCFETs) are compared in this research. The proposed ohmic recess process reduces the parasitic ohmic alloyed resistance caused by the undoped Schottky layer, and therefore improves the device performance in terms of dc, rf, source resistance as well as power characteristics. Owing to a lower source and drain resistances characteristic, OR-DCFETs demonstrated a high device current, high power-added efficiency (PAE), and better device linearity, which are very important for microwave power applications.
- 社団法人電子情報通信学会の論文
- 2006-06-26
著者
-
Chiu Hsien
Dept. Of Electronic Engineering Chang Gung University
-
Chan Chien-liang
Dep. Of Electronic Engineering Minghsin University Of Science And Technology University
-
Liao Chien
Dep. Of Electrical Engineering National Central University
-
LIAO Chien-Nan
Dept. of Electrical Engineering, National Central University
-
CHIEN Feng-Tso
Dept. of Electronic Engineering, Feng Chia University
-
CHIU Hsien-Chin
Dept. of Electronic Engineering, Chang Gung University
-
Chan Chien-Liang
Dept. of Electronic Engineering, Feng Chia University
-
Yin Jin-Mu
Dept. of Electronic Engineering, Feng Chia University
-
Chien Feng
Dept. of Electronics Engineering, National Chiao Tung University
-
Chiu H‐c
National Central Univ. Jungli Twn
-
Yin Jin-mu
Dept. Of Electronic Engineering Feng Chia University
-
Chien Feng‐tso
Dep. Of Electronic Engineering Feng Chia University
-
Chien Feng-tso
The R&d Dept. Chino-excel Technology Corp.:the Department Of Electrical Engineering Feng Chia Un
-
Liao Chien-nan
Dept. Of Electrical Engineering National Central University
-
Liao Chien-nan
Department Of Electrical Engineering National Central University
-
Fang Chin-mu
Department Of Electronic Engineering Feng-chia University
-
Fang Chin-mu
Dept. Of Electronic Engineering Feng-chia University
-
Chen Chii-wen
Dep. Of Electronic Engineering Minghsin University Of Science And Technology University
-
Chan Chien-liang
Dept. Of Electronic Engineering Feng-chia University
-
Chiu Hsien-chin
The Department Of Electrical Engineering National Central University
-
Chien Feng
Dept. Of Electronic Engineering Feng-chia University
関連論文
- A Novel Power MOSFET Structure with Shallow Junction Dual Well Design(Compound Semiconductor and Power Devices,Fundamentals and Applications of Advanced Semiconductor Devices)
- High Current, High Power, and High Linearity Ohmic Recess InGaP/InGaAs Doped Channel FETs(Session 7B Compound Semiconductor Devices III,AWAD2006)
- High Current, High Power, and High Linearity Ohmic Recess InGaP/InGaAs Doped Channel FETs(Session 7B Compound Semiconductor Devices III)
- High Current, High Power, and High Linearity Ohmic Recess InGaP/InGaAs Doped Channel FETs
- High Performance Power MOSFETs by Wing-Cell Structure Design(Si Devices and Processes,Fundamental and Application of Advanced Semiconductor Devices)
- High Performance Power MOSFETs by Wing-cell Structure Design (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- High Performance Power MOSFETs by Wing-cell Structure Design (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- Device Linearity and Gate Voltage Swing Improvement by Al_Ga_As/In_Ga_As Double Doped-Channel Design (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000)
- High Ruggedness Power MOSFET Design by a Self-Align p^+ Process(Power Devices, Fundamental and Application of Advanced Semiconductor Devices)
- A Novel High Ruggedness Power MOSFET With a Planar Oxide Deep P+ Implant Structure
- InGaP/InGaAs DCFETs with Drain and Source Recess Process
- High Ruggedness Power MOSFET Design by a Self-Align P+ Process(Session A7 High Power Devices)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Boron Penetration study of P channel Power MOSFET for Low Gate Driving Application(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- High Ruggedness Power MOSFET Design by a Self-Align P+ Process(Session A7 High Power Devices)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Boron Penetration study of P channel Power MOSFET for Low Gate Driving Application(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Boron Penetration study of P channel Power MOSFET for Low Gate Driving Application
- A Novel Power MOSFET Structure with Split P-well and Split Poly Design
- A Novel Power MOSFET Structure with Split P-well and Split Poly Design
- The Analysis of the Floating Field Limiting Ring and Field Plate(Session6: Power Devices)
- Improvement of the Leakage by Second Thermal Oxidation Process Power Trench Gate MOSFET(Session6: Power Devices)
- The Analysis of the Floating Field Limiting Ring and Field Plate(Session6: Power Devices)
- Improvement of the Leakage by Second Thermal Oxidation Process Power Trench Gate MOSFET(Session6: Power Devices)
- Low gate leakage current HEMTs by a new airbridge gate and a liquid oxidization surface (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Low gate leakage current HEMTs by a new airbridge gate and a liquid oxidization surface (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- High Power Density and Large Voltage Swing of Enhancement-Mode Al_Ga_As/InGaAs Pseudomorphic High Electron Mobility Transistor for 3.5 V L-Band Applications
- High Power In_0.49Ga_0.51P/In_0.15Ga_0.85As Heterostructure Doped-Channel FETs (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000)
- The Study of Drain Alloy Time and Temperature for Antimony Substrate Vertical High Voltage Power MOSFETs(Session 6B Power Devices,AWAD2006)
- The Study of Drain Alloy Time and Temperature for Antimony Substrate Vertical High Voltage Power MOSFETs(Session 6B Power Devices,AWAD2006)
- High ruggedness power MOSFET design by a source RTA process (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- High ruggedness power MOSFET design by a source RTA process (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- High performance bottom-gated poly-Si thin film transistors employing novel extended metal-pad (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- High performance bottom-gated poly-Si thin film transistors employing novel extended metal-pad (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Low switching loss power MOSFET with dual gate structure (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Low switching loss power MOSFET with dual gate structure (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- A Novel Power MOSFET Structure with Shallow Junction Dual Well Design(Session 6B Power Devices,AWAD2006)
- A Novel Power MOSFET Structure with Shallow Junction Dual Well Design(Session 6B Power Devices,AWAD2006)
- Study of Drain Alloy for Antimony Substrate Vertical High Voltage Power Metal Oxide Semiconductor Field Effect Transistors