Impact of Physical Vapor Deposition-Based In situ Fabrication Method on Metal/High-$k$ Gate Stacks

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We proposed an in situ method for fabricating metal/high-$k$ gate stacks. High-quality Hf silicate gate dielectrics were formed by utilizing a solid phase interface reaction (SPIR) between a metal Hf layer and an SiO2 underlayer, and TiN electrodes were continuously grown on the gate dielectrics using a low-damage sputtering system without exposure to air. We investigated the optimum SPIR conditions for TiN/HfSiO gate stacks, such as the thicknesses of the metal Hf and oxide underlayers, in situ annealing temperature, and oxygen pressure. The results indicate that the in situ method can be used to precisely control the SPIR to form silicate films and improve the electrical properties at metal/high-$k$ interfaces. We demonstrated that the scaling of equivalent oxide thickness (EOT) was achieved and that the carbon impurity content at the gate stacks was successfully reduced by in situ silicate formation and continuous electrode deposition. As a consequence, we obtained excellent EOT versus gate leakage characteristics and succeeded in improving the hysteresis of capacitance–voltage curves for the TiN/HfSiO gate stacks.
2007-04-30