Back-end Integration of Pt/BST/Pt Capacitor for ULSI DRAM Applications

概要

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(Ba, Sr)TiO_3 is a strong candidate as the capacitor dielectrics for ULSI DRAM. For successful application of BST into ULSI DRAM, it is neccessary to develop high quality BST film and oxidation resistant barrier[1, 2]. Another important issue to be stressed in the integration of the BST capacitor is the electrical degradation during back-end process[3]. Capacitance, dielectric loss and leakage current density can be seriously degraded by electrode roughening and mechanical stress induced by upper dielectric layer. In this study, a 0.3 × 0.8μm^2 sized BST capacitor with Pt electrodes is fabricated, and, several factors related with the electrical degradation, such as the electrode roughness, upper dielectric layer, and postannealing conditions are investigated. The degradation of the electrical properties during back-end process is avoided by novel processes.
社団法人電子情報通信学会の論文
1998-07-23