Back-end Integration of Pt/BST/Pt Capacitor for ULSI DRAM Applications
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概要
- 論文の詳細を見る
(Ba, Sr)TiO_3 is a strong candidate as the capacitor dielectrics for ULSI DRAM. For successful application of BST into ULSI DRAM, it is neccessary to develop high quality BST film and oxidation resistant barrier[1, 2]. Another important issue to be stressed in the integration of the BST capacitor is the electrical degradation during back-end process[3]. Capacitance, dielectric loss and leakage current density can be seriously degraded by electrode roughening and mechanical stress induced by upper dielectric layer. In this study, a 0.3 × 0.8μm^2 sized BST capacitor with Pt electrodes is fabricated, and, several factors related with the electrical degradation, such as the electrode roughness, upper dielectric layer, and postannealing conditions are investigated. The degradation of the electrical properties during back-end process is avoided by novel processes.
- 社団法人電子情報通信学会の論文
- 1998-07-23
著者
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Lee Moon
Samsung Electronics Co. Semiconductor R&d Center Memory Process Development Team
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Lee Sang
Samsung Electronics Co. Ltd. Gyunggi Kor
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Lee Moon
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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Kim W
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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Lee M
Samsung Electronics Co. Ltd. Kyungki‐do Kor
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Lee K
Etri Taejon Kor
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Lee Ki
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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Yoo Cha-young
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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Lim Han
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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Kang Chang
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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Joo S
Samsung Electronics Co. Ltd. Kyungki‐do Kor
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Lee S
Samsung Electronics Co. Ltd. Kyungki‐do Kor
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Lee Sang
Process Development Team Semiconductor R&d Center Samsung Electronics Co. Ltd
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Lee Byoung
Samsung Electronics, Co., Semiconductor R&D Center, Memory Process Development Team
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Kim Wan
Samsung Electronics, Co., Semiconductor R&D Center, Memory Process Development Team
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Joo Suk
Samsung Electronics, Co., Semiconductor R&D Center, Memory Process Development Team
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Horii Hideki
Samsung Electronics, Co., Semiconductor R&D Center, Memory Process Development Team
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Park Hong
Samsung Electronics, Co., Semiconductor R&D Center, Memory Process Development Team
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Lee K
Semiconductor R&d Center Samsung Electronics Co. Ltd
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Lee S
Samsung Electronics Co. Ltd. Kyungki Kor
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HORII Hideki
Process Development Team, Memory Division, Samsung Electronics Co., Ltd.
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Lee Moon
Semiconductor R&d Samsung Electronics Co. Ltd.
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Park Hong
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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LEE Byoung
ASET EUV Laboratory
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Kim Wan
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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Joo Suk
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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Lee Byoung
Samsung Electronics Co. Semiconductor R & D Center Memory Process Development Team
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Horii Hideki
Process Development Team Memory Division Samsung Electronics Co. Ltd.
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Kang Chang
Samsung Electronics Co. Semiconductor R&d Center Memory Process Development Team 2
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Lee S.I.
Semiconductor R&D Division, Samsung Electronics Co., Ltd.
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Lee Sang
Samsung Electro-Mechanics Co., Ltd., 314, Maetan-3-Dong, Paldal-Gu, Suwon-Si, Gyunggi-Do, 442-743, Republic of Korea
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