Design Considerations for Patterned Wafer Bonding

概要

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In patterned wafer bonding process, the debonded area occurring at bonding interface results from the poor wafer flatness of patterned wafer or from the different bonding speed in each position of the wafer. By reducing pressure when bonding occurs and by using interlayer films, we observed that the bondability of the patterned wafers enhances. In such a case, the result was also experimentally proved to be effective for the suppression of particles. In order to obtain the accurate alignment of the bonded wafers we specially designed a vacuum bonding machine, which has a function of self-controlled alignment mechanism (Rotating angle of <0.01°, side margin of <100 μm). Finally, we obtained void free thin silicon on insulator (SOI) device layer not affecting in the successive lithography process.
社団法人応用物理学会の論文
1997-03-30