An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT) (Special Issue on New Concept Device and Novel Architecture LSIs)

スポンサーリンク

概要

• 論文の詳細を見る

• A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.957% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.

• 1997-07-25

著者

• MASUOKA Fujio

  Research Institute of Electrical Communication, Tohoku University

• Endoh T

  Tohoku Univ. Sendai‐shi Jpn

• Endoh T

  Tohoku Univ. Sendai Jpn

• Endoh Tetsuo

  Research Institute Of Electrical Communication Tohoku University

• Masuoka F

  Tohoku Univ. Sendai Jpn

• Masuoka Fujio

  Research Institute Of Electrical Communication Tohoku University

• Masuoka Fujio

  The Reserch Institute Of Electrical Communication Tohoku University

• NAKAMURA Tairiku

  Research Institute of Electrical Communication, Tohoku University

• Masuoka F

  Research Institute Of Electrical Communication Tohoku University

• NAKAMURA Tomonori

  Tohoku University

• Nakamura Tairiku

  Research Institute Of Electrical Communication Tohoku University

• Endoh T

  Research Institute Of Electrical Communication Tohoku University

• Nakamura T

  Department Of Bioengineering And Robotics Tohoku University

関連論文

• Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip
• A New Wafer Scale Chip-on-Chip (W-COC) Packaging Technology Using Adhesive Injection Method
• Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering(Semiconductor Materials and Devices)
• A High Performance Voltage Down Converter (VDC) Using New Flexible Control Technology of Driving Current
• Evaluation of the Voltage Down Converter(VDC)with Low Ratio of consuming Current to Load Current in DC/AC Operation Mode
• Hydrogen-Controlled Crystallinity of 3C-SiC Film on Si(001) Grown with Monomethylsilane
• Ge-Dot Formation on Si(111)-7 × 7 Surface with C Predeposition Using Monomethylsilane
• High-Performance Buried-Gate Surrounding Gate Transistor for Future Three-Dimensional Devices
• An Analysis of Program and Erase Mechanisms for Floating Channel Type Surrounding Gate Transistor Flash Memory Cells(Semiconductor Materials and Devices)
• New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond
• Buried Gate Type SGT Flash Memory(The IEICE Transactions (published in Japanese) Vol. J86-C, No.5 (Electronics))
• Influence of Silicon Wafer Loading Ambient on Chemical Composition and Thickness Uniformity of Sub-5-nm-Thick Oxide Films : Surfaces, Interfaces, and Films
• The Analysis of the Stacked-Surrounding Gate Transistor(S-SGT)DRAM for the High Speed and Low Voltage Operation
• New Write/Erase Operation Technology for Flash EEPROM Cells to Improve the Read Disturb Characteristics
• New Reduction Mechanism of the Stress Leakage Current Based on the Deactivation of Step Tunneling Sites for Thin Oxide Films
• An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT) (Special Issue on New Concept Device and Novel Architecture LSIs)
• An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT) (Special Issue on New Concept Device and Novel Architecture LSIs)
• A Novel Programming Method Using a Reverse Polarity Pulse in Flash EEPROMs (Special Issue on ULSI Memory Technology)
• New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell
• Data Retention Characteristics of Flash Memory Cells after Write and Erase Cycling (Special Section on High Speed and High Density Multi Functional LSI Memories)
• A New Reverse Base Current (RBC) of the Bipolar Transistor Induced by Impact Ionization
• Biologically Inspired Vision Chip with Three Dimensional Structure(Special Issue on Integrated Systems with New Concepts)
• An Advanced NAND-Structure Cell Technology for Reliable 3.3 V 64 Mb Electrically Erasable and Programmable Read Only Memories (EEPROMs)
• The Object-Space Parallel Processing of the Multipass Rendering Method on the (Μπ)^2 with a Distributed-Frame Buffer System
• (Mπ)^2: A Hierarchical Parallel Processing System for the Multipass Rendering Method (Special Issue on Architectures Algorithms and Networks for Massively parallel Computing)
• Congestion Control Scheme in Multimedia Networks
• Increasing Network Throughput in Token Ring by IP Scheme
• Modeling of the Hole Current Caused by Fowler-Nordheim Tunneling through Thin Oxides
• Physical Origin of Stress-Induced Leakage Currents in Ultra-Thin Silicon Dioxide Films(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
• Study of 30-nm Double-Gate MOSFET with Halo Implantation Technology Using a Two-Dimensional Device Simulator(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
• Thin-Film Deposition of Silicon-Incorporated Diamond-Like Carbon by Plasma-Enhanced Chemical Vapor Deposition Using Monomethylsilane as a Silicon Source
• Fabrication of Nanometer Silicon Pillars for Buried-Gate-Type Surrounding Gate Transistor by Silicon Quasi-Isotropic Etching
• Study of Self-Heating in Si Nano Structure for Floating Body-Surround Gate Transistor with High-$k$ Dielectric Films
• New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond

もっと見る 閉じる

スポンサーリンク