Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering(Semiconductor Materials and Devices)
スポンサーリンク
概要
- 論文の詳細を見る
This paper shows that the Surrounding Gate Transistor (SGT) can be scaled down to decananometer gate lengths by using an intrinsically-doped body and gate work function engineering. Strong gate controllability is an essential characteristics of the SGT. However, by using an intrinsically-doped body, the SGT can realize a higher carrier mobility and stronger gate controllability of the silicon body. Then, in order to adjust the threshold voltage, it is necessary to adopt gate work function engineering in which a metal or metal silicide gate is used. Using a three-dimensional (3D) device simulator, we analyze the short-channel effects and current characteristics of the SGT. We compare the device characteristics of the SGT to those of the Tri-gate transistor and Double-Gate (DG) MOSFET. When the silicon pillar diameter (or silicon body thickness) is 10nm, the gate length is 20nm, and the oxide thickness is 1nm, the SGT shows a subthreshold swing of 63mV/dec and a DIBL of -17mV, whereas the Tri-gate transistor and the DG MOSFET show a subthreshold swing of 71mV/dec and 77mV/dec, respectively, and a DIBL of -47mV and -75mV, respectively. By adjusting the value of the gate work function, we define the off current at V_G=0V and V_D=1V. When the off current is set at 1pA/μm, the SGT can realize a high on current of 1020μA/μm at V_G=1V and V_D=1V. Moreover, the on current of the SGT is 21% larger than that of the Tri-gate transistor and 52% larger than that of the DG MOSFET. Therefore, the SGT can be scaled reliably toward the decananometer gate length for high-speed and low-power ULSI.
- 社団法人電子情報通信学会の論文
- 2006-04-01
著者
-
Yamamoto Yasue
System Lsi Technology Development Center Corporate System Lsi Development Division Semiconductor Com
-
Yamamoto Yasue
System Lsi Technology Development Center Corporate System Lsi Division Semiconductor Company Matsush
-
Yamamoto Yasue
Research Institute Of Electrical Communication Tohoku University
-
HIDAKA Takeshi
Research Institute of Electrical Communication, Tohoku University
-
NAKAMURA Hiroki
Research Institute of Electrical Communication, Tohoku University
-
SAKURABA Hiroshi
Research Institute of Electrical Communication, Tohoku University
-
MASUOKA Fujio
Research Institute of Electrical Communication, Tohoku University
-
Masuoka F
Tohoku Univ. Sendai Jpn
-
Masuoka Fujio
Research Institute Of Electrical Communication Tohoku University
-
Masuoka Fujio
The Reserch Institute Of Electrical Communication Tohoku University
-
Masuoka F
Research Institute Of Electrical Communication Tohoku University
-
Sakuraba Hiroshi
Research Institute Of Electrical Communication Tohoku University
-
Hidaka Takeshi
Research Institute Of Electrical Communication Tohoku University
-
Nakamura Hiroki
Research Institute Of Electrical Communication Tohoku University
-
NAKAMURA HIROKI
Research Division, Hitachi Plant Engineering & Construction Corporation
関連論文
- Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering(Semiconductor Materials and Devices)
- A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI(Semiconductor Materials and Devices)
- A High Performance Voltage Down Converter (VDC) Using New Flexible Control Technology of Driving Current
- Evaluation of the Voltage Down Converter(VDC)with Low Ratio of consuming Current to Load Current in DC/AC Operation Mode
- High-Performance Buried-Gate Surrounding Gate Transistor for Future Three-Dimensional Devices
- An Analysis of Program and Erase Mechanisms for Floating Channel Type Surrounding Gate Transistor Flash Memory Cells(Semiconductor Materials and Devices)
- New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond
- Buried Gate Type SGT Flash Memory(The IEICE Transactions (published in Japanese) Vol. J86-C, No.5 (Electronics))
- Influence of Silicon Wafer Loading Ambient on Chemical Composition and Thickness Uniformity of Sub-5-nm-Thick Oxide Films : Surfaces, Interfaces, and Films
- The Analysis of the Stacked-Surrounding Gate Transistor(S-SGT)DRAM for the High Speed and Low Voltage Operation
- New Write/Erase Operation Technology for Flash EEPROM Cells to Improve the Read Disturb Characteristics
- New Reduction Mechanism of the Stress Leakage Current Based on the Deactivation of Step Tunneling Sites for Thin Oxide Films
- An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT) (Special Issue on New Concept Device and Novel Architecture LSIs)
- An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT) (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Novel Programming Method Using a Reverse Polarity Pulse in Flash EEPROMs (Special Issue on ULSI Memory Technology)
- New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell
- Data Retention Characteristics of Flash Memory Cells after Write and Erase Cycling (Special Section on High Speed and High Density Multi Functional LSI Memories)
- A New Reverse Base Current (RBC) of the Bipolar Transistor Induced by Impact Ionization
- Immobilization of Nitrifying Bacteria by Polyethylene Glycol Prepolymer
- Immobilization of Activated Sludge by the Acrylamide Method
- Sensitivities of Some Characteristics of Nuclear Equilibrium State to One-Group Constants
- Fabrication of Nanometer Silicon Pillars for Buried-Gate-Type Surrounding Gate Transistor by Silicon Quasi-Isotropic Etching
- New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond