New Write/Erase Operation Technology for Flash EEPROM Cells to Improve the Read Disturb Characteristics

スポンサーリンク

概要

• 論文の詳細を見る

• This paper describes the new write/erase operation methods in order to improve the read disturb characteristics for Flash EEPROM cells which are written by channel hot electron injection and erased by F-N tunneling emission from the floating gate to the substrate. The new operation methods is either applying a reverse polarity pulse after each erase pulse or applying a series of shorter erase pulses instead of a long single erase pulse. It is confirmed that by using the above operation methods, the leakage current can be suppressed, and then the read disturb life time after 10^5 cycles write/erase operation is more than 10 times longer in comparison with the conventional method. This memory cell by using the proposed write/erase operation method has superior potential for application to 256 Mbit Flash memories as beyond.

• 1997-10-25

著者

• MASUOKA Fujio

  Research Institute of Electrical Communication, Tohoku University

• Endoh T

  Tohoku Univ. Sendai‐shi Jpn

• Endoh T

  Tohoku Univ. Sendai Jpn

• Endoh Tetsuo

  Research Institute Of Electrical Communication Tohoku University

• Masuoka F

  Tohoku Univ. Sendai Jpn

• Masuoka Fujio

  Research Institute Of Electrical Communication Tohoku University

• Masuoka Fujio

  The Reserch Institute Of Electrical Communication Tohoku University

• Masuoka F

  Research Institute Of Electrical Communication Tohoku University

• IIZUKA Hirohisa

  Microelectronics Engineering Lab. Toshiba

• SHIROTA Riichirou

  Microelectronics Engineering Lab. Toshiba

• Shirota Riichiro

  Microelectronics Engineering Lab. Toshiba

• Shirota Riichiro

  Toshiba Research And Development Center Ulsi Research Laboratories

• Endoh T

  Research Institute Of Electrical Communication Tohoku University

• Iizuka Hirohisa

  Toyota Central Research & Development Labs. Inc.

関連論文

• Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering(Semiconductor Materials and Devices)
• A High Performance Voltage Down Converter (VDC) Using New Flexible Control Technology of Driving Current
• Evaluation of the Voltage Down Converter(VDC)with Low Ratio of consuming Current to Load Current in DC/AC Operation Mode
• Hydrogen-Controlled Crystallinity of 3C-SiC Film on Si(001) Grown with Monomethylsilane
• Ge-Dot Formation on Si(111)-7 × 7 Surface with C Predeposition Using Monomethylsilane
• High-Performance Buried-Gate Surrounding Gate Transistor for Future Three-Dimensional Devices
• An Analysis of Program and Erase Mechanisms for Floating Channel Type Surrounding Gate Transistor Flash Memory Cells(Semiconductor Materials and Devices)
• New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond
• Buried Gate Type SGT Flash Memory(The IEICE Transactions (published in Japanese) Vol. J86-C, No.5 (Electronics))
• Influence of Silicon Wafer Loading Ambient on Chemical Composition and Thickness Uniformity of Sub-5-nm-Thick Oxide Films : Surfaces, Interfaces, and Films
• The Analysis of the Stacked-Surrounding Gate Transistor(S-SGT)DRAM for the High Speed and Low Voltage Operation
• New Write/Erase Operation Technology for Flash EEPROM Cells to Improve the Read Disturb Characteristics
• New Reduction Mechanism of the Stress Leakage Current Based on the Deactivation of Step Tunneling Sites for Thin Oxide Films
• An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT) (Special Issue on New Concept Device and Novel Architecture LSIs)
• An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT) (Special Issue on New Concept Device and Novel Architecture LSIs)
• A Novel Programming Method Using a Reverse Polarity Pulse in Flash EEPROMs (Special Issue on ULSI Memory Technology)
• New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell
• Data Retention Characteristics of Flash Memory Cells after Write and Erase Cycling (Special Section on High Speed and High Density Multi Functional LSI Memories)
• A New Reverse Base Current (RBC) of the Bipolar Transistor Induced by Impact Ionization
• An Advanced NAND-Structure Cell Technology for Reliable 3.3 V 64 Mb Electrically Erasable and Programmable Read Only Memories (EEPROMs)
• Millimeter-Wave Microstrip Array Antenna for Automotive Radars(Antenna and Propagation)
• Millimeter-Wave Microstrip Line to Waveguide Transition Fabricated on a Single Layer Dielectric Substrate
• Modeling of the Hole Current Caused by Fowler-Nordheim Tunneling through Thin Oxides
• Dynamics of Longitudinal Component in Ordered Spin Systems
• Physical Origin of Stress-Induced Leakage Currents in Ultra-Thin Silicon Dioxide Films(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
• Study of 30-nm Double-Gate MOSFET with Halo Implantation Technology Using a Two-Dimensional Device Simulator(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
• Thin-Film Deposition of Silicon-Incorporated Diamond-Like Carbon by Plasma-Enhanced Chemical Vapor Deposition Using Monomethylsilane as a Silicon Source
• Fabrication of Nanometer Silicon Pillars for Buried-Gate-Type Surrounding Gate Transistor by Silicon Quasi-Isotropic Etching
• Study of Self-Heating in Si Nano Structure for Floating Body-Surround Gate Transistor with High-$k$ Dielectric Films
• New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond

もっと見る 閉じる

スポンサーリンク