An Advanced NAND-Structure Cell Technology for Reliable 3.3 V 64 Mb Electrically Erasable and Programmable Read Only Memories (EEPROMs)
スポンサーリンク
概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 1994-01-30
著者
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Sakui K
Toshiba Corp. Yokohama
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Endoh T
Tohoku Univ. Sendai‐shi Jpn
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Endoh T
Tohoku Univ. Sendai Jpn
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Hemink Gertjan
Ulsi Research Center Toshiba Corporation
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IIZUKA Hirohisa
ULSI Research Laboratories, Toshiba R&D Center
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ENDOH Tetsuo
ULSI Research Laboratories, Toshiba R&D Center
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ARITOME Seiichi
ULSI Research Laboratories, Toshiba R&D Center
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SHIROTA Riichiro
ULSI Research Laboratories, Toshiba R&D Center
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HATAKEYAMA Ikuo
ULSI Research Center, TOSHIBA Corporation
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YAMAGUCHI Tetsuya
ULSI Research Center, TOSHIBA Corporation
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SHUTO Susumu
ULSI Research Center, TOSHIBA Corporation
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MARUYAMA Tooru
ULSI Research Center, TOSHIBA Corporation
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WATANABE Hiroshi
ULSI Research Center, TOSHIBA Corporation
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SAKUI Koji
ULSI Research Center, TOSHIBA Corporation
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TANAKA Tomoharu
ULSI Research Center, TOSHIBA Corporation
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MOMODOMI Masaki
ULSI Research Center, TOSHIBA Corporation
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Shirota Riichiro
Microelectronics Engineering Lab. Toshiba
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Aritome Seiichi
Ulsi Research Laboratories Toshiba R&d Center
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Shirota Riichiro
Toshiba Research And Development Center Ulsi Research Laboratories
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Shuto Susumu
Ulsi Research Center Toshiba Corporation
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Endoh T
Research Institute Of Electrical Communication Tohoku University
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Maruyama Tooru
Ulsi Research Center Toshiba Corporation
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Iizuka Hirohisa
Toyota Central Research & Development Labs. Inc.
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Momodomi Masaki
Ulsi Research Center Toshiba Corporation
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Tanaka Tomoharu
Ulsi Research Center Toshiba Corporation
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Hatakeyama Ikuo
Ulsi Research Center Toshiba Corporation
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Yamaguchi Tetsuya
Ulsi Research Center Toshiba Corporation
関連論文
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- Evaluation of the Voltage Down Converter(VDC)with Low Ratio of consuming Current to Load Current in DC/AC Operation Mode
- High-Performance Buried-Gate Surrounding Gate Transistor for Future Three-Dimensional Devices
- An Analysis of Program and Erase Mechanisms for Floating Channel Type Surrounding Gate Transistor Flash Memory Cells(Semiconductor Materials and Devices)
- Buried Gate Type SGT Flash Memory(The IEICE Transactions (published in Japanese) Vol. J86-C, No.5 (Electronics))
- The Analysis of the Stacked-Surrounding Gate Transistor(S-SGT)DRAM for the High Speed and Low Voltage Operation
- New Write/Erase Operation Technology for Flash EEPROM Cells to Improve the Read Disturb Characteristics
- New Reduction Mechanism of the Stress Leakage Current Based on the Deactivation of Step Tunneling Sites for Thin Oxide Films
- An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT) (Special Issue on New Concept Device and Novel Architecture LSIs)
- An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT) (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Novel Programming Method Using a Reverse Polarity Pulse in Flash EEPROMs (Special Issue on ULSI Memory Technology)
- Data Retention Characteristics of Flash Memory Cells after Write and Erase Cycling (Special Section on High Speed and High Density Multi Functional LSI Memories)
- A New Reverse Base Current (RBC) of the Bipolar Transistor Induced by Impact Ionization
- A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices (Special Issue on Microelectronic Test Structure)
- An Advanced NAND-Structure Cell Technology for Reliable 3.3 V 64 Mb Electrically Erasable and Programmable Read Only Memories (EEPROMs)
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- Millimeter-Wave Microstrip Line to Waveguide Transition Fabricated on a Single Layer Dielectric Substrate
- Modeling of the Hole Current Caused by Fowler-Nordheim Tunneling through Thin Oxides
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