A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices (Special Issue on Microelectronic Test Structure)

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概要

• 論文の詳細を見る

• A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest threshold voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.

• 社団法人電子情報通信学会の論文
• 1996-02-25

著者

• Sakui K

  Toshiba Corp. Yokohama

• Hazama Hiroaki

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• MIYAMOTO Jun-ichi

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• HIMENO Toshihiko

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• MATSUKAWA Naohiro

  Semiconductor Quality Assurance Department, TOSHIBA CORPORATION

• SAKUI Koji

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• OSHIKIRI Masamitsu

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• MASUDA Kazunori

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• KANDA Kazushige

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• ITOH Yasuo

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• Miyamoto Jun-ichi

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Miyamoto J

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Kanda Kazushige

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Itoh Y

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Oshikiri Masamitsu

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Himeno Toshihiko

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Matsukawa Naohiro

  Semiconductor Quality Assurance Department Toshiba Corporation

• Masuda K

  Nec Corp. Kawasaki‐shi Jpn

関連論文

• A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories (Special Issue on ULSI Memory Technology)
• Data Retention Characteristics of Flash Memory Cells after Write and Erase Cycling (Special Section on High Speed and High Density Multi Functional LSI Memories)
• A New Reverse Base Current (RBC) of the Bipolar Transistor Induced by Impact Ionization
• A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices (Special Issue on Microelectronic Test Structure)
• An Advanced NAND-Structure Cell Technology for Reliable 3.3 V 64 Mb Electrically Erasable and Programmable Read Only Memories (EEPROMs)
• A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
• Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement (Special Issue on LSI Memories)
• Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90nm Technology and Beyond (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)

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