Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement (Special Issue on LSI Memories)

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概要

• 論文の詳細を見る

• The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.

• 社団法人電子情報通信学会の論文
• 1993-11-25

著者

• MIYAMOTO Jun-ichi

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• IMAMIYA Ken-ichi

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• Imamiya Ken-ichi

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Miyamoto Jun-ichi

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Tomita Naoto

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Ohtsuka Nobuaki

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• Iyama Yumiko

  TOSHIBA Microelectronics Corporation

• Ohtsuka Nobuaki

  Semiconductor Device Engineering Laboratory Toshiba Corporation

関連論文

• A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories (Special Issue on ULSI Memory Technology)
• A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices (Special Issue on Microelectronic Test Structure)
• Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement (Special Issue on LSI Memories)

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