Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90nm Technology and Beyond (Low Power Techniques, <Special Section> VLSI Design Technology in the Sub-100nm Era)
スポンサーリンク
概要
- 論文の詳細を見る
Circuit techniques for realizing low-voltage and lowpower SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-μA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5mA at 50MHz, 0.5V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9V.
- 社団法人電子情報通信学会の論文
著者
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TSUKADA Toshiro
Semiconductor Technology Academic Research Center
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ITOH Yasuo
Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION
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Yamashita Takahiro
Semiconductor Technology Academic Research Center (starc):presently With Toshiba Corp.
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Minematsu Isao
Semiconductor Technology Academic Research Center (starc):presently With Renesas Technology Corp.
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Hashimoto Yasuyuki
Semiconductor Technology Academic Research Center (starc):presently With Rohm Cp. Ltd.
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ISHIBASHI Koichiro
Semiconductor Technology Academic Research Center (STARC)
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FUJIMOTO Tetsuya
Semiconductor Technology Academic Research Center (STARC)
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OKADA Hiroyuki
Semiconductor Technology Academic Research Center (STARC)
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ARIMA Yukio
Semiconductor Technology Academic Research Center (STARC)
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SAKATA Kohji
Semiconductor Technology Academic Research Center (STARC)
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TODA Haruki
Semiconductor Technology Academic Research Center (STARC)
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ICHIHASHI Motoi
Semiconductor Technology Academic Research Center (STARC)
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KOMATSU Yoshihide
Semiconductor Technology Academic Research Center (STARC)
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HAGIWARA Masato
Semiconductor Technology Academic Research Center (STARC)
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Toda Haruki
Semiconductor Technology Academic Research Center (starc):presently With Toshiba Corp.
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Arima Yukio
Semiconductor Technology Academic Research Center (starc):presently With Matsushita Electric Industr
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Sakata Kohji
Semiconductor Technology Academic Research Center (starc):presently With Sanyo Electric Co. Ltd.
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Ichihashi Motoi
Semiconductor Technology Academic Research Center (starc):presently With Renesas Technology Corp.
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Hagiwara Masato
Semiconductor Technology Academic Research Center (starc):presently With Renesas Technology Corp.
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Fujimoto Tetsuya
Semiconductor Technology Academic Research Center (starc):presently With Sharp Corp.
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Komatsu Yoshihide
Semiconductor Technology Academic Research Center (starc):presently With Matsushita Electric Industr
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Ishibashi Koichiro
Semiconductor Technology Academic Research Center (starc):presently With Renesas Technology Corp.
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Itoh Yasuo
Semiconductor Technology Academic Research Center (starc):presently With Toshiba Microelectronics Co
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Tsukada Toshiro
Semiconductor Technology Academic Research Center (starc)
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Tsukada Toshiro
Semiconductor & Integrated Circuits Group Hitachi Lid.
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Okada Hiroyuki
Semiconductor Technology Academic Research Center (starc):presently With Nec Corp.
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- Approaches to Reducing Digital-Noise Coupling in CMOS Mixed-Signal LSIs (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
- Substrate Noise Reduction Using Active Guard Band Filters in Mixed-Signal Integrated Circuits (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
- Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90nm Technology and Beyond (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling (Special Section on Analog Circuit Techniques and Related Topics)
- Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond (Soft Error, VLSI Design Technology in the Sub-100nm Era)
- Experimental Study on Fully Integrated Active Guard Band Filters for Suppressing Substrate Noise in Sub-Micron CMOS Processes for System-on-a-Chip(Regular Section)