Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond (Soft Error, <Special Section> VLSI Design Technology in the Sub-100nm Era)

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概要

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• This paper describes a soft error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. The storage node of the latch is separated into three electrodes and a soft error on one node is collected by the other two nodes despite the large amount and long-lasting influx of radiation-induced charges. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130-nm 2-well, 3-well, and also 90-nm 2-well CMOS processes. The proposed circuit demonstrated immunity that was two orders higher through an irradiation test using alpha-particles, and immunity that was one order higher through neutron irradiation. We also demonstrated forward body bias control, which improves alpha-ray immunity by 26% for a standard latch and achieves 44 times improvement in the proposed latch.

• 社団法人電子情報通信学会の論文

著者

• ISHIBASHI Koichiro

  Semiconductor Technology Academic Research Center (STARC)

• ARIMA Yukio

  Semiconductor Technology Academic Research Center (STARC)

• KOMATSU Yoshihide

  Semiconductor Technology Academic Research Center (STARC)

• Arima Yukio

  Semiconductor Technology Academic Research Center (starc):presently With Matsushita Electric Industr

• Komatsu Yoshihide

  Semiconductor Technology Academic Research Center (starc):presently With Matsushita Electric Industr

• Ishibashi Koichiro

  Semiconductor Technology Academic Research Center (starc):presently With Renesas Technology Corp.

関連論文

• Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90nm Technology and Beyond (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
• Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond (Soft Error, VLSI Design Technology in the Sub-100nm Era)

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