A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling (Special Section on Analog Circuit Techniques and Related Topics)

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概要

• 論文の詳細を見る

• In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods.

• 社団法人電子情報通信学会の論文
• 1999-02-25

著者

• Funaba Seiji

  Semiconductor & Integrated Circuits Group Hitachi Lid.

• TSUKADA Toshiro

  Semiconductor Technology Academic Research Center

• KITAGAWA Akihiro

  Semiconductor and Integrated Circuits Group, Hitachi, Ltd.

• YOKOMIZO Goichi

  Semiconductor & Integrated Circuits Group, Hitachi, Lid.

• Yokomizo Goichi

  Semiconductor & Integrated Circuits Group Hitachi Lid.

• Tsukada Toshiro

  Semiconductor & Integrated Circuits Group Hitachi Lid.

• Kitagawa Akihiro

  Semiconductor & Integrated Circuits Group Hitachi Lid.

関連論文

• Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation
• A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm(Analog Circuits and Related SoC Integration Technologies)
• Complex Bandpass ΔΣAD Modulator Architecture without I, Q-Path Crossing Layout(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• A 10-bit 3-Msample/s CMOS Multipath Multibit Cyclic ADC (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
• High-Speed Continuous-Time Subsampling Bandpass ΔΣAD Modulator Architecture Employing Radio Frequency DAC(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• Approaches to Reducing Digital-Noise Coupling in CMOS Mixed-Signal LSIs (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
• Substrate Noise Reduction Using Active Guard Band Filters in Mixed-Signal Integrated Circuits (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
• Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90nm Technology and Beyond (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
• A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling (Special Section on Analog Circuit Techniques and Related Topics)
• Experimental Study on Fully Integrated Active Guard Band Filters for Suppressing Substrate Noise in Sub-Micron CMOS Processes for System-on-a-Chip(Regular Section)

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