A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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概要

• 論文の詳細を見る

• A 16-Mb flash EEPROM has been developed based on the 0.6-μm triple-well double-poly-si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 μm × 1.7 μm, and the die size has resulted in 7.7 mm × 17.32 mm.

• 社団法人電子情報通信学会の論文
• 1994-05-25

著者

• OSHIKIRI Masamitsu

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• Umezawa Akira

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Yamane Tomoko

  Toshiba Microelectronics Corporation

• Kuriyama Masao

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Hiura Yohei

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Atsumi Shigeru

  Semiconductor Device Engineering Laboratory, Toshiba Corporation

• Banba Hironori

  Semiconductor Device Engineering Laboratory, Toshiba Corporation

• Naruke Kiyomi

  Semiconductor Device Engineering Laboratory, Toshiba Corporation

• Yamada Seiji

  Semiconductor Device Engineering Laboratory, Toshiba Corporation

• Ohshima Yoichi

  Semiconductor Device Engineering Laboratory, Toshiba Corporation

• Yoshikawa Kuniyoshi

  Semiconductor Device Engineering Laboratory, Toshiba Corporation

• Atsumi S

  Hiroshima Univ. Hiroshima Jpn

• Naruke Kiyomi

  Semiconductor Device Engineering Laboratory Toshiba Corporation:memory Division Toshiba Corporation

• Banba Hironori

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Ohshima Yoichi

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Oshikiri Masamitsu

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Yoshikawa Kuniyoshi

  Semiconductor Device Engineering Laboratory Toshiba Corporation

• Yamada Seiji

  Semiconductor Device Engineering Laboratory Toshiba Corporation

関連論文

• A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices (Special Issue on Microelectronic Test Structure)
• A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
• A Novel High-Density EEPROM Cell Using a Polysilicon-Gate Hole (POLE) Structure Suitable for Low-Power Applications

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