A Novel High-Density EEPROM Cell Using a Polysilicon-Gate Hole (POLE) Structure Suitable for Low-Power Applications
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概要
- 論文の詳細を見る
A novel-high density electrically erasable and programmable read only memory (EEPROM) cell technology is proposed. The new cell utilizing a polysilicon-gate hole (POLE) structure can be used to reduce the channel length and the substrate current I sub by 2 orders of magnitude in comparison with a conventional stacked-gate flash cell by isolating the charge transfer region and thus strongly reducing band-to-band tunneling current. A 36 µm2 cell, which is 20% smaller than that of a floating gate tunnel oxide (FLOTOX) type EEPROM, with a 0.6 µm design rule can be realized. Furthermore, stable write and erase (W/E) operations are confirmed, and the characteristics of 1 million W/E cycles and 10-year data retention have been achieved.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 1996-02-28
著者
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Noda Jun-ichiro
Semiconductor Group Toshiba Corp.
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Yoshikawa Kuniyoshi
Semiconductor Device Engineering Laboratory Toshiba Corporation
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TOHYAMA Daisuke
Toshiba Microelectronics Corp.
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Noda Jun-ichiro
Semiconductor Group, Toshiba Corp., 1 Komukai Toshiba-cho, Saiwaiku, Kawasaki, 210, Japan
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Takebuchi Masataka
Semiconductor Group, Toshiba Corp., 1 Komukai Toshiba-cho, Saiwaiku, Kawasaki, 210, Japan
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Ueno Shu
Semiconductor Group, Toshiba Corp., 1 Komukai Toshiba-cho, Saiwaiku, Kawasaki, 210, Japan
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Osari Kanji
Semiconductor Group, Toshiba Corp., 1 Komukai Toshiba-cho, Saiwaiku, Kawasaki, 210, Japan
関連論文
- A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Novel High Density EEPROM Cells Using Poly-Gate Hole (POLE) Structure Suitable for Low Power Applications
- A Novel High-Density EEPROM Cell Using a Polysilicon-Gate Hole (POLE) Structure Suitable for Low-Power Applications