Nonvolatile Memory Characteristics with Embedded Hemispherical Silicon Nanocrystals

スポンサーリンク

概要

• 論文の詳細を見る

• Silicon nanocrystal-embedded memories were fabricated by using the thermal agglomeration of an ultrathin (1.5–1.8 nm) amorphous silicon (a-Si) film. The a-Si was deposited on a 4-nm tunnel-oxide layer by electron beam evaporation and subsequently annealed in situ at 850 °C for 5 min. Hemispherical Si nanocrystals were self-assembled, and nonvolatile memories were fabricated after depositing a 17-nm control-oxide layer. A threshold voltage window of 0.9 V was achieved under write/erase (W/E) voltages of $\pm 10$ V, and good endurance characteristics up to $10^{4}$ cycles were exhibited. Increasing W/E voltages created a large memory window (${>}2.7$ V), and the retention characteristics showed little temperature dependence up to 85 °C.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2007-10-15

著者

• Ma Ming-wen

  Institute And Department Of Electronics Engineering National Chiao Tung University

• Chao Tien-sheng

  Department Of Electrophysics National Chiao Tung University

• Yang Tsung-yu

  Department Of Electrical Engineering National Central University

• Lei Tan-fu

  Institute And Department Of Electronics Engineering National Chiao Tung University

• Wu Woei-Cherng

  Department of Electronic Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan, Tao-Yuan 333, Taiwan

• Lei Tan-Fu

  Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan

• Yang Tsung-Yu

  Department of Electrophysics, National Chiao Tung University, Hsinchu 300, Taiwan

• Chen Jian-Hao

  Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan

• Landheer Dolf

  Institute for Microstructural Sciences, National Research Council of Canada, Ottawa, Ontario K1A 0R6, Canada

• Wu Xiaohua

  Institute for Microstructural Sciences, National Research Council of Canada, Ottawa, Ontario K1A 0R6, Canada

• Ma Ming-Wen

  Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan

関連論文

• Combined Negative Bias Temperature Instability and Hot Carrier Stress Effects in Low Temperature Poly-Si Thin Film Transistors
• A Novel Process-Compatible Floating Channel Crystallization Technique to Fabricate High-Performance Poly-Si TFTs
• Improvement of Electrical Characteristics for Novel Fluorine-Incorporated Poly-Si TFTs with TiN Gate Electrode and Pr_2O_3 Gate Dielectric
• Local Strained Channel nMOSFETs by Different Poly-Si Gate and SiN Capping Layer Thicknesses : Mobility, Simulation, Size Dependence, and Hot Carrier Stress
• Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices
• High-κ Material Sidewall with Source/Drain-to-Gate Non-overlapped Structure for Low Standby Power Applications
• Performance Improvement of Nickel Salicided n-Type Metal Oxide Semiconductor Field Effect Transistors by Nitrogen Implantation : Semiconductors
• Reduction of Nickel-Silicided Junction Leakage by Nitrogen Ion Implantation : Semiconductors
• The Characteristics and Reliability of Multi-channel Poly-Si TFTs
• NBTI-Stress Induced Grain-Boundary Degradation in Low-Temperature Poly-Si Thin-Film Transistors
• Improving Electrical Characteristics of High-k NiTiO Dielectric with Nitrogen Ion Implantation
• Characteristics of Polycrystalline Silicon Thin-Film Transistors with Electrical Source/Drain Extensions Induced by a Bottom Sub-Gate
• High Efficiency Open Collector Adaptive Bias SiGe HBT Differential Power Amplifier(Microwaves, Millimeter-Waves)
• Determination of Ultrathin Oxide Thickness by Subthreshold Swing
• High-$k$ HfxGdyOz Charge Trapping Layer in Silicon–Oxide–Nitride–Silicon Type Nonvolatile Memory by In situ Radio Frequency Dual-Sputtering Method
• Electrical Enhancement of Polycrystalline Silicon Thin-Film Transistors Using Fluorinated Silicate Glass Passivation Layer
• Robust Data Retention and Superior Endurance of Silicon-Oxide-Nitride-Oxide-Silicon-Type Nonvolatile Memory with NH-Plasma-Treated and Pd-Nanocrystal-Embedded Charge Storage Layer (Special Issue : Solid State Devices and Materials (2))
• Novel Method of Converting Metallic-Type Carbon Nanotubes to Semiconducting-Type Carbon Nanotube Field-Effect Transistors
• Hot Carrier Degradations of Dynamic Threshold Silicon on Insulator p-Type Metal–Oxide–Semiconductor Field Effect Transistors
• The Effects of Dielectric Type and Thickness on the Characteristics of Dynamic Threshold Metal Oxide Semiconductor Transistors
• Performance Enhancement by Local Strain in $\langle 110\rangle$ Channel n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on (111) Substrate
• Nonvolatile Flash Memory Devices Using CeO2 Nanocrystal Trapping Layer for Two-Bit per Cell Applications
• Systematical Study of Reliability Issues in Plasma-Nitrided and Thermally Nitrided Oxides for Advanced Dual-Gate Oxide p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors
• Nonvolatile Memory Characteristics with Embedded Hemispherical Silicon Nanocrystals
• High-$\kappa$ Material Sidewall with Source/Drain-to-Gate Non-overlapped Structure for Low Standby Power Applications
• Crystal Orientation and Nitrogen Effects on the Carrier Mobility of p-Type Metal Oxide Semiconductor Field Effect Transistor with Ultra Thin Gate Dielectrics
• High-Performance Solid-Phase Crystallized Polycrystalline Silicon Thin-Film Transistors with Floating-Channel Structure
• Suppression of Boron Penetration in P+-Poly-SiGe Gate P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Using NH3-Nitrided and N2O-Grown Gate Oxides

もっと見る 閉じる

スポンサーリンク