Electrical Enhancement of Polycrystalline Silicon Thin-Film Transistors Using Fluorinated Silicate Glass Passivation Layer

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概要

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• Polycrystalline silicon thin-film transistors (poly-Si TFTs) with a fluorinated silicate glass (FSG) passivation layer are proposed and demonstrated in this study. Experimental results reveal that the electrical characteristics can be improved by the incorporation of appropriate amounts of fluorine in the poly-Si film. The poly-Si TFTs with a FSG passivation layer show a high on-current, a low off-state gate-induced drain leakage (GIDL) current, a high field-effect mobility, and a suppressed kink effect, compared with the poly-Si TFTs with an undoped SiO2 passivation layer. The presence of incorporated fluorine atoms from the FSG passivation layer in the poly-Si channel film can passivate the trap states at the grain boundaries. Furthermore, the incorporation of fluorine atoms can form stronger Si–F bonds near the source and drain sides to enhance the immunity against hot-carrier stress. In addition, the proposed poly-Si TFTs are easy to fabricate, have a low production cost, and are realized using a process compatible with modern TFT manufacturing technology.

• 2008-02-25

著者

• Chang Chia-wen

  Institute Of Electronics National Chiao-tung University

• Huang Jiun-jia

  Institute Of Electronics National Chiao-tung University

• Deng Chih-kang

  Institute Of Electronics National Chiao-tung University

• Lei Tan-fu

  Institute And Department Of Electronics Engineering National Chiao Tung University

• Lei Tan-Fu

  Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 30050, Taiwan

• Deng Chih-Kang

  Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 30050, Taiwan

• Wang Tong-Yi

  Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 30050, Taiwan

• Huang Jiun-Jia

  Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 30050, Taiwan

関連論文

• Combined Negative Bias Temperature Instability and Hot Carrier Stress Effects in Low Temperature Poly-Si Thin Film Transistors
• A Novel Process-Compatible Floating Channel Crystallization Technique to Fabricate High-Performance Poly-Si TFTs
• Improvement of Electrical Characteristics for Novel Fluorine-Incorporated Poly-Si TFTs with TiN Gate Electrode and Pr_2O_3 Gate Dielectric
• Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices
• The Characteristics and Reliability of Multi-channel Poly-Si TFTs
• Optimization on Layout Structures of LTPS TFTs for On-Panel ESD Protection Design
• NBTI-Stress Induced Grain-Boundary Degradation in Low-Temperature Poly-Si Thin-Film Transistors
• Characteristics of Polycrystalline Silicon Thin-Film Transistors with Electrical Source/Drain Extensions Induced by a Bottom Sub-Gate
• Electrical Enhancement of Polycrystalline Silicon Thin-Film Transistors Using Fluorinated Silicate Glass Passivation Layer
• Nonvolatile Flash Memory Devices Using CeO2 Nanocrystal Trapping Layer for Two-Bit per Cell Applications
• Electrical Properties of High-$\kappa$ Praseodymium Oxide Polycrystalline Silicon Thin-Film Transistors with Nitrogen Implantation
• Nonvolatile Memory Characteristics with Embedded Hemispherical Silicon Nanocrystals
• High-$\kappa$ Material Sidewall with Source/Drain-to-Gate Non-overlapped Structure for Low Standby Power Applications
• High-Performance Solid-Phase Crystallized Polycrystalline Silicon Thin-Film Transistors with Floating-Channel Structure

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