Influences of Annealing Temperature on Characteristics of Ge p-Channel Metal Oxide Semiconductor Field Effect Transistors with ZrO2 Gate Dielectrics

概要

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The dependence of gate leakage current and p+/n-junction characteristics on annealing temperature is investigated comprehensively in order to obtain good electrical characteristics of Ge p-channel metal oxide semiconductor field effect transistors (p-MOSFETs) with ZrO2 gate dielectrics. The upper limit of annealing temperature is restricted to 500 °C to preserve low gate leakage. Gate leakage current remains low even after Ge incorporation into ZrO2, because ZrO2/Ge gate stacks retain their band alignment to as high as 500 °C. The degradation of gate leakage at the high temperature of 700 °C is due to the emergence of void regions near the interface in the Ge substrate. On the other hand, the lower limit of the annealing temperature is restricted to 400 °C in order to activate dopant boron sufficiently. Good rectifying diode characteristics lead to promising p-MOSFET performance, such as an $S$-factor of 80 mV/decade. The effective hole mobility of the ZrO2/Ge gate stack without an intentional interfacial layer after annealing at the optimized temperature is as high as 100 cm2/(V$\cdot$s).
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2006-07-15