Re-Examination of Performance and Reliability Degradation in Metal--Oxide--Nitride--Oxide--Semiconductor Memory with Ultrathin SiN Charge Trap Layers
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概要
- 論文の詳細を見る
We demonstrated that the degradation of program characteristics in metal--oxide--nitride--oxide--semiconductor (MONOS) devices consisting of an ultrathin ({\sim}2 nm) SiN charge trap layer is due to a decrease in the electron capture efficiency, instead of a reduction in the number of available trap sites. From the data retention properties with applied gate bias voltage, we clarified that charge loss through the tunnel layer during data retention becomes more significant with decreasing SiN thickness. These results indicate that to improve the performance and reliability of MONOS devices with an ultrathin SiN charge trap layer, measures must be taken to enhance the capture cross section of the traps and to inhibit carrier motion in the SiN layer simultaneously.
- 2012-04-25
著者
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Koyama Masato
Advanced Lsi Technology Laboratory Corporate R & D Center Toshiba Corporation
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Sakuma Kiwamu
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Oda Masato
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Fujii Shosuke
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Kusai Haruka
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Morota Misako
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Kusai Haruka
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Morota Misako
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Koyama Masato
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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