Ultra-Shallow Junction Formation with Antimony Implantation(Special Issue on Advanced Sub-0.1μm CMOS Devices)
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概要
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Ultra shallow low-resistive junction formation has been investigated for sub-100-nm MOSFETs using antimony implantation. The pileup at the Si/SiO_2 interface and the resulting dopant loss during annealing is a common obstacle for antimony and arsenic to reduce junction sheet resistance. Though implanted arsenic gives rise to pileup even with a few seconds duration RTA (Rapid Thermal Annealing), antimony pileup was suppressed with the RTA at relatively low temperature, such as 800℃ or 900℃. As a result, low sheet resistance of 260Ω/sq. was obtained for a 24nm depth junction with antimony. These results indicate that antimony is superior to arsenic as a dopant for ultra shallow extension formation. However, increase in antimony concentration above 1 x 10^<20>cm^<-3> gives rise to precipitation and it limits the sheet resistance reduction of the antimony doped junctions. Redistribution behaviors of antimony relating to the pileup and the precipitation are discussed utilizing SIMS (Secondary Ion Mass Spectrometry) depth profiles.
- 社団法人電子情報通信学会の論文
- 2002-05-01
著者
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Shibahara Kentaro
Research Center For Nanodevices And Systems Hiroshima University
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Shibahara Kentaro
Reseach Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan
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