Phosphorus-Assisted Low-Energy Arsenic Implantation Technology for N-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Source/Drain Formation Process
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概要
- 論文の詳細を見る
In this paper, we present phosphorous-assisted low-energy arsenic implantation technology for forming n+ source/drain regions. Low-energy arsenic implantation suppresses transient enhanced diffusion of boron, and this relieves the reverse short-channel effect. Combined with phosphorous implantation, this technology minimizes both the junction-leakage current and the gate polysilicon depletion (polydepletion) effect. A 130-nm-gate-length n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) has been fabricated with this technology, which exhibits improved $I_{\text{on}}$–$I_{\text{off}}$ and $V_{\text{th}}$ roll-off characteristics.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-05-15
著者
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Yokoyama Shin
Research Center For Integrated Systems Hiroshima University
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SHISHIGUCHI Seiichi
Association of Super-advanced Electronics Technologies (ASET)
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Imai Kiyotaka
Ulsi Device Development Laboratories Nec Corporation
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Shibahara Kentaro
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan
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Shibahara Kentaro
Reseach Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan
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Imai Kiyotaka
ULSI Device Development Division, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
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IMAI Kiyotaka
ULSI Device Development Division, NEC Corporation
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