真空ピンチャックの吸着特性(第1報) : 裏面うねりの表面平坦度への影響

概要

論文の詳細を見る
Fabrication of ULSI devices requires a 12" silicon wafer to have a site flatness below 0.1 μm. Vacuum pin chucks have been used for planarizing in optical lithography or for final polishing. This paper describes the influence of the back-surface waviness on wafer flatness. Pin support during clamping reduces the effect of the dust, but degrades wafer flatness. It is shown that degradation of wafer flatness is caused by a smaller number of contact pins between the pin top and the wafer's back surface, and improper contact conditions. It is also shown that there is no practical problem in using a 700-μm-thick silicon wafer with a 1-mm-pitch-pin chuck during polishing.
公益社団法人精密工学会の論文
1998-10-05