Evaluation of Interface Property and DC Characteristics Enhancement in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Using Stress Memorization Technique
スポンサーリンク
概要
- 論文の詳細を見る
In this letter, the advanced 40 nm technology n-channel metal–oxide–semiconductor field-effect transistor devices using the stress memorization technique (SMT) are presented. We demonstrate that SMT process would not affect the electrical characteristics of devices and can introduce higher tensile stress on channels, which enhances drive current. Through charge pumping measurement, it can be verified that SMT does not affect Si/SiO2 interface quality. Moreover, SMT-induced higher tensile stress decreases not only scattering coefficient but also tunneling attenuation length, resulting in smaller input-referred noise, which represents an intrinsic advantage of low-frequency noise performance.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2010-09-25
著者
-
Wu San
Department Of Electronic Engineering Cheng Shiu University
-
Chang Shoou
Institute Of Microelectronics & Department Of Electrical Engineering Center For Micro/nano Scien
-
Kuo Cheng
Institute of Microelectronics and Department of Electrical Engineering, Advanced Optoelectronic Technology Center, Center for Micro/Nano Science and Technology, National Cheng Kung University, No. 1 Ta Hseuh Road, Tainan 701, Taiwan, R.O.C.
-
Huang Yao
Institute of Microelectronics and Department of Electrical Engineering, Advanced Optoelectronic Technology Center, Center for Micro/Nano Science and Technology, National Cheng Kung University, No. 1 Ta Hseuh Road, Tainan 701, Taiwan, R.O.C.
-
Wu San
Department of Electronic Engineering, Cheng Shiu University, No. 840, Chengching Rd., Niaosong Township, Kaohsiung County 833, Taiwan, R.O.C.
-
Cheng Osbert
Central R&D Division, United Microelectronics Corporation, Tainan 741, Taiwan, R.O.C.
-
Cheng Osbert
Central R&D Division, United Microelectronics Corporation (UMC), Hsinchu 30077, Taiwan, R.O.C.
-
Cheng Yao
Central R&D Division, United Microelectronics Corporation, Tainan 741, Taiwan, R.O.C.
-
Huang Po
Institute of Microelectronics and Department of Electrical Engineering, Advanced Optoelectronic Technology Center, Center for Micro/Nano Science and Technology, National Cheng Kung University, No. 1 Ta Hseuh Road, Tainan 701, Taiwan, R.O.C.
-
Chang Ching
Institute of Microelectronics and Department of Electrical Engineering, Advanced Optoelectronic Technology Center, Center for Micro/Nano Science and Technology, National Cheng Kung University, No. 1 Ta Hseuh Road, Tainan 701, Taiwan, R.O.C.
関連論文
- A Novel Triple δ-Doped SiGe Heterostructure Field-Effect Transistor
- Device Linear Improvement Using SiGe/Si Heterostructure Delta-Doped-Channel Field-Effect Transistors
- Low Temperature Activation of Mg-Doped GaN in O_2 Ambient : Semiconductors
- Investigation of Transport Mechanism for Strained Si n Metal-Oxide-Semiconductor Field-Effect Transistor Grown on Multi-Layer Substrate
- Strained Si_Ge_x Normal-Graded Channel P-Type Metal Oxide Semiconductor Field Effect Transistor
- High-Performance Doped-Channel Field-Effect Transistor Using Graded SiGe Channel
- Investigation of Impact Ionization in Strained-Si nMOSFETs
- A New Silicon Field-Effect Transistors with Two-Hole-Transport-Mode (HTM) Channels Grown by Molecular Beam Epitaxy (MBE)
- Effects of Interfacial Oxide Layer for the Ta_2O_5 Capacitor After High-Temperature Annealing
- Surface Characteristics, Optical and Electrical Properties on Sol-Gel Synthesized Sn-Doped ZnO Thin Film
- Tolerance Design of Passive Filter Circuits Using Genetic Programming(Electronic Circuits)
- Vertical High Quality Mirrorlike Facet of GaN-Based Device by Reactive Ion Etching
- Characterization of Oxide Tarps in 28 nm p-Type Metal--Oxide--Semiconductor Field-Effect Transistors with Tip-Shaped SiGe Source/Drain Based on Random Telegraph Noise
- Impact of SiN on Performance in Novel Complementary Metal–Oxide–Semiconductor Architecture Using Substrate Strained-SiGe and Mechanical Strained-Si Technology
- P-Type Enhancement-Mode SiGe Doped-Channel Field-Effect Transistor
- Characterization of Oxide Traps in 28 nm n-Type Metal--Oxide--Semiconductor Field-Effect Transistors with Different Uniaxial Tensile Stresses Utilizing Random Telegraph Noise
- Effect of Annealing Process on Trap Properties in High-k/Metal Gate n-Channel Metal--Oxide--Semiconductor Field-Effect Transistors through Low-Frequency Noise and Random Telegraph Noise Characterization
- Evaluation of Interface Property and DC Characteristics Enhancement in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Using Stress Memorization Technique
- Hole Confinement and $1/ f$ Noise Characteristics of SiGe Double-Quantum-Well p-Type Metal–Oxide–Semiconductor Field-Effect Transistors
- Characterization of Oxide Traps in 28 nm n-Type Metal-Oxide-Semiconductor Field-Effect Transistors with Different Uniaxial Tensile Stresses Utilizing Random Telegraph Noise (Special Issue : Solid State Devices and Materials)
- Optimized Si-Cap Layer Thickness for Tensile-Strained-Si/ Compressively Strained SiGe Dual-Channel Transistors in 0.13 μm Complementary Metal Oxide Semiconductor Technology
- Investigation of Transport Mechanism for Strained Si n Metal–Oxide–Semiconductor Field-Effect Transistor Grown on Multi-Layer Substrate