Optimized Si-Cap Layer Thickness for Tensile-Strained-Si/ Compressively Strained SiGe Dual-Channel Transistors in 0.13 μm Complementary Metal Oxide Semiconductor Technology
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概要
- 論文の詳細を見る
We report the fabrication of a tensile-strained-Si/compressively strained Si0.72Ge0.28 dual-channel n-type metal–oxide–semiconductor field-effect transistor (NMOSFET) and p-type metal–oxide–semiconductor field-effect transistor (PMOSFET), which were grown on a relaxed Si0.8Ge0.2 virtual substrate using the 0.13 μm CMOS process and we integrate both devices at the same wafer. It is found that a device based on such a structure that is good for optimizing NMOSFET and PMOSFET performance uses a thinner Si-cap layer of 5 nm for PMOSFET and a thicker Si-cap layer of approximately 15 nm for NMOSFET; this offers the most efficient enhancement of carrier mobility. By constraining the Si-cap layer thickness, the current drives of the N and PMOSFETs were increased by 16% and 12%, respectively, for channel lengths down to 0.13 um.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 2005-09-10
著者
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Wu San
Department Of Electronic Engineering Cheng Shiu University
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Chang Shoou
Institute Of Microelectronics & Department Of Electrical Engineering Center For Micro/nano Scien
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WANG Yen
Institute of Microelectronics and Department of Electrical Engineering, National Cheng Kung Universi
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- Investigation of Transport Mechanism for Strained Si n Metal–Oxide–Semiconductor Field-Effect Transistor Grown on Multi-Layer Substrate