A Dynamically Configurable NoC Test Access Mechanism (VLSI設計技術)
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概要
- 論文の詳細を見る
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols...) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T^2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.
- 2011-11-21
著者
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Namba Kazuteru
Chiba Univ. Chiba‐shi Jpn
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Ito Hideo
Chiba Univ. Chiba‐shi Jpn
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Ito Hideo
Graduate School Of Advanced Integration Sci. Chiba Univ.
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Namba Kazuteru
Graduate School Of Advanced Integration Sci. Chiba Univ.
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SBIAI Takieddine
Graduate School of Advanced Integration Science, Chiba University
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